Partial block erase for a three dimensional (3D) memory
A method includes, at a non-volatile memory having a three dimensional (3D) memory configuration, performing an erase operation. Performing the erase operation includes providing a first control signal to isolate a first portion of a string of the non-volatile memory from a second portion of the string. Performing the erase operation further includes providing a first erase signal to erase the second portion of the string while data is maintained at the first portion of the string.
1. A data storage device comprising:
a non-volatile memory having a three dimensional (3D) memory configuration that is monolithically formed in one or more physical levels of arrays of memory cells having an active area disposed above a silicon substrate, the non-volatile memory including circuitry associated with operation of the memory cells, wherein the non-volatile memory comprises:
a string including a plurality of storage elements, wherein the string includes a first portion and a second portion; and
a switch coupled to the string, wherein the switch is configurable to isolate the first portion of the string from the second portion of the string based on a control signal.
2. The data storage device of claim 1 , wherein the switch comprises a metal-oxide semiconductor (MOS) transistor.
3. The data storage device of claim 1 , further comprising erase circuitry configured, when the first portion is isolated from the second portion, to perform a first erase operation on the second portion of the string to erase data at the second portion while maintaining data at the first portion of the string.
4. The data storage device of claim 1 , wherein a first bias terminal is located at a first end of the first portion, and wherein a second bias terminal is located at a second end of the first portion.
5. The data storage device of claim 4 , wherein a third bias terminal is located at a first end of the second portion, and wherein a fourth bias terminal is located at a second end of the second portion.
6. The data storage device of claim 1 , further comprising a controller coupled to the non-volatile memory, wherein the controller is configured to determine whether to enable the switch to couple the first portion and the second portion or to disable the switch to decouple the first portion from the second portion.
7. The data storage device of claim 6 , wherein each storage element of the plurality of storage elements corresponds to a wordline, and wherein each wordline is coupled to a different current sensor.
8. The data storage device of claim 7 , wherein, during an erase operation to erase a particular wordline, a particular current sensor corresponding to the particular wordline determines an amount of current through the particular wordline, and wherein an indication of the amount of current is provided to a controller.
9. A data storage device comprising:
a non-volatile memory comprising a string including a plurality of storage elements, wherein the string includes a first portion and a second portion; and
a controller configured to generate control signals, wherein the control signals include a first control signal to cause the first portion to be coupled to the second portion and a second control signal to cause the first portion to be decoupled from the second portion.
10. The data storage device of claim 9 , wherein the non-volatile memory further comprises a switch coupled to the string, wherein the switch is configurable to electrically couple the first portion and the second portion of the string responsive to the first control signal, and wherein the switch is configurable to isolate the first portion from the second portion of the string responsive to the second control signal.
11. The data storage device of claim 10 , wherein the switch comprises a metal-oxide semiconductor (MOS) transistor.
12. The data storage device of claim 10 , wherein each storage element of the plurality of storage elements corresponds to a wordline, and wherein each wordline is coupled to a different current sensor.
13. The data storage device of claim 10 , wherein the non-volatile memory has a three dimensional (3D) memory configuration that is monolithically formed in one or more physical levels disposed above a silicon substrate.
14. An apparatus comprising:
a non-volatile memory having a three dimensional (3D) memory configuration that is monolithically formed in one or more physical levels above a silicon substrate, wherein the non-volatile memory comprises:
means for providing a first control signal to isolate a first portion of a string of the non-volatile memory from a second portion of the string; and
means for providing a first erase signal to erase the second portion of the string while data is maintained at the first portion of the string.
15. The apparatus of claim 14 , wherein the string includes a third portion.
16. The apparatus of claim 15 , wherein the apparatus further comprises:
first means for coupling and decoupling the first portion of the string to the second portion of the string; and
second means for coupling and decoupling the second portion of the string to a third portion of the string.
17. The apparatus of claim 14 , wherein the first portion is included in a first physical level of the one or more physical levels, and wherein the second portion is included in a second physical level of the one or more physical levels.
18. The apparatus of claim 14 , wherein the first portion includes a first set of one or more storage elements, and wherein the second portion includes a second set of one or more storage elements.
19. The apparatus of claim 18 , wherein the first set of one or more storage elements and the second set of one or more storage elements include the same number of storage elements.
20. The apparatus of claim 18 , wherein the first set of one or more storage elements includes a single storage element.