NAND string containing self-aligned control gate sidewall cladding

1. A NAND string, comprising:

a semiconductor channel;

a tunnel dielectric located over a semiconductor channel;

a plurality of floating gates separated by trenches located over the tunnel dielectric;

a plurality of blocking dielectric regions separated by the trenches, each of the plurality of blocking dielectric regions is located over at least a respective one of the plurality of floating gates;

a plurality of control gates separated by the trenches, each of the plurality of control gates is located over a respective one of the plurality of blocking dielectric regions; and

a plurality of metal-first material compound sidewall spacers located on sidewalls of the plurality of control gates;

wherein:

the sidewall spacers protrude into the trenches beyond sidewalls of respective floating gates located under the control gates;

each control gate comprises a first sidewall spacer on a first control gate sidewall and a second sidewall spacer on a second control gate sidewall;

a width of each control gate comprises a distance from the first control gate sidewall to the second control gate sidewall;

each floating gate comprises a first floating gate sidewall exposed in a first trench and a second floating gate sidewall exposed in a second trench;

a width of each control gate comprises a distance from the first floating gate sidewall to the second floating gate sidewall; and

the width of each floating gate is greater than the width of each respective control gate located above the respective floating gate.

2. The NAND string of claim 1 , wherein the first material comprises a Group IV material and the metal-first material compound sidewall spacers comprise metal-Group IV compound sidewall spacers.

3. The NAND string of claim 2 , wherein the metal comprises tungsten, then first material comprises silicon, and the metal-first material compound sidewall spacers comprise tungsten silicide sidewall spacers.

4. The NAND string of claim 3 , wherein the plurality of control gates each comprises a lower polysilicon portion and an upper tungsten or tungsten nitride portion.

5. A NAND string, comprising:

a semiconductor channel;

a tunnel dielectric located over a semiconductor channel;

a plurality of floating gates separated by trenches located over the tunnel dielectric;

a plurality of blocking dielectric regions separated by the trenches, each of the plurality of blocking dielectric regions is located over at least a respective one of the plurality of floating gates;

a plurality of control gates separated by the trenches, each of the plurality of control gates is located over a respective one of the plurality of blocking dielectric regions; and

a plurality of metal silicide sidewall spacers located on sidewalls of the plurality of control gates,

wherein:

each control gate comprises a first metal silicide sidewall spacer on a first control gate sidewall and a second metal silicide sidewall spacer on a second control gate sidewall;

a width of each control gate comprises a distance from the first control gate sidewall to the second control gate sidewall;

each floating gate comprises a first floating gate sidewall exposed in a first trench and a second floating gate sidewall exposed in a second trench;

a width of each floating gate comprises a distance from the first floating gate sidewall to the second floating gate sidewall; and

the width of each floating gate is greater than the width of each respective control gate located above the respective floating gate.

6. The NAND string of claim 5 , wherein the metal silicide sidewall spacers comprise tungsten silicide sidewall spacers.

7. The NAND string of claim 6 , wherein the plurality of control gates each comprises a lower polysilicon portion and an upper tungsten or tungsten nitride portion.

8. The NAND string of claim 5 , wherein the plurality of control gates each comprises a metal, a metal nitride, a metal oxide or a doped semiconductor.