Barrier layer stack for bit line air gap formation
Air gaps are formed between conductive metal lines that have an inner barrier layer and an outer barrier layer. An etch step to remove sacrificial material is performed under a first set of process conditions producing a byproduct that suppresses further etching. A byproduct removal step performed under a second set of process conditions removes the byproduct.
1. A method of forming an air gap between adjacent conductive lines comprising:
forming a plurality of trenches in a dielectric layer that is formed of a dielectric material;
subsequently forming a first barrier layer in the plurality of trenches;
subsequently forming a second barrier layer over the first barrier layer; and
subsequently filling the plurality of trenches with a conductive metal to form bit lines;
subsequently removing dielectric material between bit lines by:
(a) performing a Chemical Dry Etching (CDE) step
under a first set of process conditions
thereby substantially etching the dielectric material and the second barrier layer simultaneously
without substantially etching the first barrier layer such that the first barrier layer extends above the dielectric material and second barrier layer,
the etching of the dielectric material under the first set of process conditions
producing a byproduct that suppresses the etching of the dielectric material; and
(b) subsequently performing a removal step
to remove the byproduct of the etching of the dielectric material in the CDE step
under a second set of process conditions.
2. The method of claim 1 wherein the second barrier layer is formed of a barrier metal; and
the first barrier layer is a nitride or an oxide of the barrier metal.
3. The method of claim 1 wherein under the first set of process conditions an etchant is supplied; and
under the second set of process conditions no etchant is supplied.
4. The method of claim 1 wherein the first set of process conditions includes a first temperature that is lower than a sublimation temperature of the byproduct, and
the second set of process conditions includes a second temperature that is higher than the sublimation temperature of the byproduct.
5. The method of claim 1 further comprising repeating steps (a) and (b) two or more times until a predetermined amount of the dielectric material is removed.
6. The method of claim 3 wherein the etchant is a gas containing fluorine (F) and hydrogen (H); and
the byproduct contains ammonium fluorosilicate ((NH 4 ) 2 SiF 6 ).
7. The method of claim 1 further comprising:
(c) subsequently, after a predetermined amount of the dielectric material is removed, performing an anneal step at a temperature that his higher than any of: a sublimation temperature of the byproduct and any temperature of the first or second sets of process conditions.
8. The method of claim 1 wherein the second barrier layer is exposed to the CDE step in an opening between the first barrier layer and the conductive metal, the opening having a width that is equal to or smaller than 1/10 of a width of exposed dielectric portions between the bit lines.
9. The method of claim 1 wherein the first barrier layer is titanium nitride (TiN), the second barrier layer is titanium (Ti), and the conductive metal is copper (Cu).
10. The method of claim 1 wherein the first set of process conditions provide equilibrium between producing the byproduct and removing the byproduct from areas between the bit lines while generating some buildup of the byproduct over exposed areas of the second barrier layer to provide suppressed etching of the second barrier layer, and wherein the second set of process conditions is sufficient to remove the byproduct only from the areas between the bit lines.
11. The method of claim 1
wherein an area of the second barrier layer is exposed to the CDE step and the area has a width along a direction perpendicular to the bit lines that is smaller than a distance between neighboring bit lines.
12. A method of forming air gaps between bit lines comprising:
(a) forming a plurality of bit lines
in a dielectric material,
an individual bit line having
an inner barrier layer and
an outer barrier layer;
(b) subsequently etching the dielectric material using an etch step
that etches the inner barrier layer,
does not significantly etch the outer barrier layer, and
etches the dielectric material
to produce a byproduct that suppresses further etching,
wherein the inner barrier layer and dielectric material are etched simultaneously such that the outer barrier layer extends above the inner barrier layer and the dielectric material;
(c) subsequently removing the byproduct using a removal step
that removes substantially all of the byproduct from over the dielectric material between bit lines and
leaves at least some of the byproduct on surfaces of the inner barrier layer; and
(d) repeating steps (b) and (c) until a predetermined amount of the dielectric material is removed.
13. The method of claim 12 wherein the inner barrier layer is formed of titanium, the outer barrier layer is formed of titanium nitride, and the byproduct is ammonium fluorosilicate ((NH 4 ) 2 SiF 6 ).
14. The method of claim 13 wherein the etch step is performed using a gas mixture that contains fluorine (F) and hydrogen (H).
15. The method of claim 14 wherein the etch step is performed at a temperature below the sublimation temperature of ammonium fluorosilicate and the removal step is performed at a temperature above the sublimation temperature of ammonium fluorosilicate.
16. The method of claim 15 further comprising, subsequent to (d), performing an anneal step to remove any remaining byproduct from over the dielectric material between bit lines and from surfaces of the inner barrier layer.
17. A method of forming air gaps between bit lines comprising:
(a) forming a plurality of bit lines
in a sacrificial layer of silicon oxide,
an individual bit line having
an inner barrier layer of titanium and
an outer barrier layer of titanium nitride;
(b) subsequently etching the silicon oxide using an etch step
that etches the titanium of the inner barrier layer,
does not significantly etch the titanium nitride of the outer barrier layer, and
etches the silicon oxide
to produce a byproduct containing ammonium fluorosilicate ((NH 4 SiF 6 ) that suppresses further etching,
wherein the titanium and silicon oxide are etched simultaneously such that the outer barrier layer extends above the inner barrier layer and the sacrificial layer;
(c) subsequently removing the byproduct using a removal step
that removes substantially all of the byproduct from over the silicon oxide between bit lines and
leaves at least some of the byproduct on surfaces of the inner barrier layer; and
(d) repeating steps (b) and (c) until a predetermined amount of the silicon oxide is removed.
18. The method of claim 17 wherein subsequent to removing the predetermined amount of silicon oxide a final removal step removes substantially all of the byproduct on surfaces of the inner barrier layer.
19. The method of claim 18 wherein the removal step applies a temperature below 150 degrees centigrade and the final removal step applies a temperature above 150 degrees centigrade.
20. The method of claim 17 wherein step (b) etches approximately 1-2 nanometers of silicon oxide and is repeated at least 10 times.