Compensation scheme for non-volatile memory
Methods for performing parallel voltage and current compensation during reading and/or writing of memory cells in a memory array are described. In some embodiments, the compensation may include adjusting a bit line voltage and/or bit line reference current applied to a memory cell based on a memory array zone, a bit line layer, and a memory cell direction associated with the memory cell. The compensation may include adjusting the bit line voltage and/or bit line reference current on a per memory cell basis depending on memory cell specific characteristics. In some embodiments, a read/write circuit for reading and/or writing a memory cell may select a bit line voltage from a plurality of bit line voltage options to be applied to the memory cell based on whether the memory cell has been characterized as a strong, weak, or typical memory cell.
1. A method for operating a non-volatile storage system, comprising:
generating a plurality of bit line voltage options associated with a read operation;
generating a plurality of bit line current options associated with the read operation;
determining a first control bit, the determining a first control bit includes acquiring a bit line address associated with a memory cell and determining whether the memory cell is located at a far end of a word line connected to the memory cell based on the bit line address;
selecting a first bit line voltage of the plurality of bit line voltage options based on the first control bit;
selecting a first bit line current of the plurality of bit line current options based on the first control bit;
determining a state of the memory cell by applying the first bit line voltage and the first bit line current to a bit line connected to the memory cell; and
outputting data associated with the state of the memory cell.
2. The method of claim 1 , wherein:
the generating a plurality of bit line voltage options includes generating the plurality of bit line voltage options based on at least one of a memory array zone associated with the memory cell or a memory cell direction associated with the memory cell.
3. The method of claim 1 , wherein:
the memory cell comprises a two-terminal memory cell.
4. The method of claim 1 , wherein:
the determining a state of the memory cell includes comparing a sensing current associated with the memory cell biased to the first bit line voltage with the first bit line current.
5. The method of claim 1 , wherein:
the memory cell is part of a three-dimensional array of memory cells.
6. The method of claim 5 , wherein:
the three-dimensional array of memory cells includes a first memory cell and a second memory cell, the first memory cell is located above the second memory cell, the second memory cell is located above a substrate.
7. The method of claim 6 , wherein:
the first memory cell and the second memory cell are arranged in a vertical column that is perpendicular to the substrate.
8. The method of claim 6 , wherein:
the first memory cell and the second memory cell are in communication with a first bit line, the first bit line is arranged in a vertical direction that is perpendicular to the substrate.
9. The method of claim 6 , wherein:
the first memory cell and the second memory cell are formed above the substrate without any intervening substrates between the first memory cell and the second memory cell.
10. A monolithic three-dimensional integrated circuit, comprising:
a memory array, the memory array includes a word line and a bit line, the memory array includes a memory cell connected to the word line and the bit line;
a plurality of voltage generators, the plurality of voltage generators generates a plurality of bit line voltage options associated with a read operation;
a plurality of current generators, the plurality of current generators generates a plurality of bit line current options associated with the read operation; and
one or more control circuits in communication with the memory array, the one or more control circuits acquire a bit line address associated with the memory cell and determine that the memory cell is located at a far end of the word line connected to the memory cell based on the bit line address, the one or more control circuits select a first bit line voltage of the plurality of bit line voltage options based on the determination that the memory cell is located at the far end of the word line, the one or more control circuits select a first bit line current of the plurality of bit line current options based on the determination that the memory cell is located at the far end of the word line, the one or more control circuits determine a state of the memory cell by causing the first bit line voltage and the first bit line current to be applied to the bit line connected to the memory cell.
11. The monolithic three-dimensional integrated circuit of claim 10 , wherein:
the plurality of voltage generators generates the plurality of bit line voltage options based on at least one of a memory array zone associated with the memory cell or a memory cell direction associated with the memory cell.
12. The monolithic three-dimensional integrated circuit of claim 10 , wherein:
the memory cell comprises a two-terminal memory cell.
13. The monolithic three-dimensional integrated circuit of claim 10 , wherein:
the one or more control circuits determine the state of the memory cell by comparing a sensing current associated with the memory cell biased to the first bit line voltage with the first bit line current.
14. The monolithic three-dimensional integrated circuit of claim 10 , wherein:
the memory array comprises a three-dimensional array of memory cells.
15. The monolithic three-dimensional integrated circuit of claim 10 , wherein:
the memory array includes a second memory cell, the memory cell is located above the second memory cell, the second memory cell is located above a substrate.
16. The monolithic three-dimensional integrated circuit of claim 15 , wherein:
the memory cell and the second memory cell are arranged in a vertical column that is perpendicular to the substrate.
17. The monolithic three-dimensional integrated circuit of claim 15 , wherein:
the memory cell and the second memory cell are in communication with the bit line, the bit line is arranged in a vertical direction that is perpendicular to the substrate.
18. The monolithic three-dimensional integrated circuit of claim 15 , wherein:
the memory cell and the second memory cell are located above the substrate without any intervening substrates between the memory cell and the second memory cell.
19. A method for operating a non-volatile storage system, comprising:
generating a plurality of bit line voltage options associated with a memory operation;
generating a plurality of bit line current options associated with the memory operation;
determining a first control bit, the determining a first control bit includes acquiring a bit line address associated with a memory cell and determining that the memory cell is located at a far end of a word line connected to the memory cell based on the bit line address;
selecting a first bit line voltage of the plurality of bit line voltage options based on the first control bit;
selecting a first bit line current of the plurality of bit line current options based on the first control bit;
determining a state of the memory cell by applying the first bit line voltage and the first bit line current to a bit line connected to the memory cell; and
outputting data based on the state of the memory cell.
20. The method of claim 19 , wherein:
the generating a plurality of bit line voltage options includes generating the plurality of bit line voltage options based on at least one of a memory array zone associated with the memory cell or a memory cell direction associated with the memory cell; and
the memory operation comprises a read operation.