Balancing programming speeds of memory cells in a 3D stacked memory
Programming techniques for a three-dimensional stacked memory device provide compensation for different intrinsic programming speeds of different groups of memory cells based on the groups' locations relative to the edge of a word line layer. A larger distance from the edge is associated with a faster programming speed. In one approach, the programming speeds are equalized by elevating a bit line voltage for the faster programming memory cells. Offset verify voltages which trigger a slow programming mode by elevating the bit line voltage can also be set based on the group locations. A programming speed can be measured during programming for a row or other group of cells to set the bit line voltage and/or the offset verify voltages. The compensation for the faster programming memory cells can also be based on their speed relative to the slower programming memory cells.
1. A method for programming in a 3D stacked memory device, comprising:
performing a programming operation for a set of memory cells, the set of memory cells is connected to a selected word line layer among a plurality of word line layers which are vertically spaced apart from one another by dielectric layers in a stack, wherein each memory cell in the set of memory cells is associated with a respective bit line among a plurality of bit lines, the selected word line layer comprises a first edge, the set of memory cells comprises a first row of memory cells at a first distance from the first edge, and a second row of memory cells at a second distance from the first edge, wherein the second distance is greater than the first distance, and the performing the programming operation comprises:
performing a plurality of program-verify iterations for the selected word line layer, each program-verify iteration of the plurality of program-verify iterations comprises a program portion followed by a verify portion, wherein at least one program-verify iteration of the plurality of program-verify iterations provides a compensation for different programming speeds of the first row of memory cells and the second row of memory cells.
2. The method of claim 1 , wherein:
the compensation is provided during the program portion by providing a bit line voltage for the second row of memory cells which is higher than a bit line voltage of the first row of memory cells.
3. The method of claim 2 , further comprising:
measuring a first programming speed of the first row of memory cells; and
measuring a second programming speed of the second row of memory cells, wherein the bit line voltage for the first row of memory cells is based on the first programming speed and the bit line voltage for the second row of memory cells is based on the second programming speed.
4. The method of claim 2 , further comprising:
measuring a first programming speed of the first row of memory cells; and
measuring a second programming speed of the second row of memory cells; and
determining a difference between the first and second programming speeds, wherein the bit line voltage for the second row of memory cells is proportional to the difference.
5. The method of claim 2 , wherein:
the bit line voltage for the first row of memory cells is 0 V.
6. The method of claim 1 , wherein:
the compensation is provided during the program portion by providing a first respective offset verify voltage of a target data state which is used to trigger a slow programming mode for the first row of memory cells and providing a second respective offset verify voltage of the target data state which is used to trigger a slow programming mode for the second row of memory cells, wherein the first respective offset verify voltage is greater than the second respective offset verify voltage.
7. The method of claim 1 , wherein:
the compensation is provided during the program portion by providing a respective offset verify voltage of a target data state which is used to trigger a slow programming mode for the second row of memory cells without providing a respective offset verify voltage of the target data state which is used to trigger a slow programming mode for the first row of memory cells.
8. The method of claim 1 , wherein:
the compensation is provided in response to measuring of a programming speed of the second row of memory cells during the programming operation, prior to the at least one program-verify iteration of the plurality of program-verify iterations.
9. The method of claim 8 , wherein:
the programming speed of the second row of memory cells is based on a number of memory cells in the second row of memory cells which reach a specified threshold voltage after a specified number of program-verify iterations of the plurality of program-verify iterations.
10. The method of claim 8 , wherein:
the programming speed of the second row of memory cells is based on a number of program-verify iterations of the plurality of program-verify iterations needed for at least a specified number of memory cells in the second row of memory cells to reach a specified threshold voltage.
11. The method of claim 1 , wherein:
the set of memory cells comprises a third row of memory cells at a third distance from the first edge;
the third distance is greater than the second distance; and
the at least one program-verify iteration of the plurality of program-verify iterations provides the compensation for different programming speeds of the first, second and third rows of memory cells.
12. The method of claim 1 , wherein:
the first edge is adjacent to a metal interconnect which provides a conductive path from a bottom of the stack to a top of the stack.