Dynamic bit line bias for programming non-volatile memory

1. A method for programming in a non-volatile storage device, comprising:

in a program operation, applying a plurality of program pulses to a word line, the word line is connected to a plurality of non-volatile storage elements, wherein each non-volatile storage element of the plurality of non-volatile storage elements is to be programmed to a respective target data state among a plurality of target data states and is associated with a respective bit line among a plurality of bit lines;

during the program operation, for each non-volatile storage element of the plurality of non-volatile storage elements, determining when a threshold voltage of the non-volatile storage element exceeds a lower verify level of the respective target data state and maintaining a respective count of a number of program pulses which are subsequently applied to the non-volatile storage element while a threshold voltage of the non-volatile storage element has not yet been verified to have exceeded a lockout verify level of the respective target data state; and

for each non-volatile storage element of the plurality of non-volatile storage elements, setting a voltage of the respective bit line at one or more stepped up levels as a function of the respective count, the one or more stepped up levels are stepped up from an initial level and allow programming of the non-volatile storage element.

2. The method of claim 1 , wherein:

the initial level allows programming of each non-volatile storage element of the plurality of non-volatile storage elements and is common for each non-volatile storage element of the plurality of non-volatile storage elements.

3. The method of claim 2 , wherein:

the initial level is 0 V.

4. The method of claim 1 , wherein:

the program operation comprises a plurality of program-verify iterations; and

threshold voltages of different non-volatile storage elements of the plurality of non-volatile storage elements which have a common target data state of the plurality of target data states exceed a lower verify level of the common target data state at different program-verify iterations of the plurality of program-verify iterations.

5. The method of claim 1 , wherein:

the program operation comprises a plurality of program-verify iterations; and

threshold voltages of different non-volatile storage elements of the plurality of non-volatile storage elements which have different target data states of the plurality of target data states exceed lower verify levels of the different target data states at different program-verify iterations of the plurality of program-verify iterations.

6. The method of claim 1 , wherein:

for at least one non-volatile storage element of the plurality of non-volatile storage elements, the voltage of the respective bit line is stepped up in at least two program pulses of the program pulses which are subsequently applied to the non-volatile storage.

7. The method of claim 1 , wherein:

for at least one non-volatile storage element of the plurality of non-volatile storage elements, the voltage of the respective bit line is stepped up in at least three program pulses.

8. The method of claim 1 , wherein for each non-volatile storage element of the plurality of non-volatile storage elements:

the respective count is maintained by storing data in a respective set of latches, each respective set of latches stores at least two bits of data to maintain the respective count; and

the respective set of latches is read before each program pulse of the program pulses which are subsequently applied to the non-volatile storage element to determine the count.

9. A non-volatile storage system, comprising:

a plurality of non-volatile storage elements connected to a word line, each non-volatile storage element of the plurality of non-volatile storage elements is to be programmed to a respective target data state among a plurality of target data states;

a respective bit line associated with each non-volatile storage element; and

a control circuit, the control circuit is configured to, in a program operation:

apply a plurality of program pulses to the word line,

for each non-volatile storage element of the plurality of non-volatile storage elements, determine when a threshold voltage of the non-volatile storage element exceeds a lower verify level of the respective target data state and maintain a respective count of a number of program pulses which are subsequently applied to the non-volatile storage element before the non-volatile storage element reaches a lockout state, and

for each non-volatile storage element of the plurality of non-volatile storage elements, set a voltage of the respective bit line at one or more stepped up levels as a function of the respective count, the one or more stepped up levels are stepped up from an initial level and allow programming of the non-volatile storage element.

10. The non-volatile storage system of claim 9 , wherein:

for at least one non-volatile storage element of the plurality of non-volatile storage elements, the respective count is at least two program pulses.

11. The non-volatile storage system of claim 9 , wherein:

for at least one non-volatile storage element of the plurality of non-volatile storage elements, the respective count is at least three program pulses.

12. The non-volatile storage system of claim 9 , further comprising, for each non-volatile storage element of the plurality of non-volatile storage elements:

a respective set of latches, wherein the respective count is maintained by storing data in the respective set of latches and each respective set of latches stores at least two bits of data to maintain the respective count.

13. A non-volatile storage system, comprising:

a plurality of non-volatile storage elements connected to a word line, each non-volatile storage element of the plurality of non-volatile storage elements is to be programmed to a respective target data state among a plurality of target data states;

a respective bit line associated with each non-volatile storage element;

a respective set of latches associated with each non-volatile storage element; and

a control circuit, the control circuit is configured to, in a program operation:

apply a plurality of program pulses to the word line, and

for each non-volatile storage element of the plurality of non-volatile storage elements, provide a fast programming mode, then a slow programming mode and then a lockout state, maintain a respective count of a number of program pulses which are applied to the non-volatile storage element in the slow programming mode and provide an adjustment of a voltage of the respective bit line based on the count during the slow programming mode.

14. The non-volatile storage system of claim 13 , wherein for each non-volatile storage element of the plurality of non-volatile storage elements, each respective set of latches comprises a plurality of bits which:

identify the respective target data state when the non-volatile storage element is in the slow programming mode and the fast programming mode,

identify the count when the non-volatile storage element is in the slow programming mode, and

indicate that the non-volatile storage element is in the lockout state, when the non-volatile storage element is in the lockout state.

15. The non-volatile storage system of claim 13 , wherein:

for non-volatile storage elements of the plurality of non-volatile storage elements which are to be programmed to a lower target data state of the plurality of target data states, the respective sets of latches comprise a first bit combination which is used to identify the lower target data state; and

for respective sets of latches associated with each non-volatile storage element of the plurality of non-volatile storage elements which is to be programmed to a higher target data state of the plurality of target data states: a second bit combination identifies the higher target data state during the fast programming mode, and the first bit combination identifies the higher target data state during at least one program pulse of the slow programming mode.

16. The non-volatile storage system of claim 15 , wherein:

for the respective sets of latches associated with the non-volatile storage elements which are to be programmed to the higher target data state: the second bit combination identifies the higher target data state during at least another program pulse of the slow programming mode.

17. The non-volatile storage system of claim 15 , wherein:

the non-volatile storage elements which are to be programmed to the lower target data state are in the lockout state during the at least one program pulse of the slow programming mode for the non-volatile storage elements which are to be programmed to the higher target data state, so that the first bit combination is no longer needed to identify the lower target data state.

18. The non-volatile storage system of claim 13 , wherein:

for at least one non-volatile storage element of the plurality of non-volatile storage elements, the voltage of the respective bit line has at least two different levels during the slow programming mode.

19. The non-volatile storage system of claim 13 , wherein:

for at least one non-volatile storage element of the plurality of non-volatile storage elements, the respective count is at least two program pulses.

20. The non-volatile storage system of claim 13 , wherein:

for at least one non-volatile storage element of the plurality of non-volatile storage elements, the respective count is at least three program pulses.