System and method for distributed computing in non-volatile memory
A system and method are disclosed for incorporating mathematical and/or logical functionality within a memory system (such as a solid state drive (SSD)). The mathematical and/or logical functionality may comprise an arithmetic logic unit (ALU). The ALU may be resident in one or both of flash memory chips or the SSD controller. When resident in the flash memory chips, a single ALU or multiple ALUs may be used. For example, a single ALU may be assigned to one, some, or each block of flash memory within the flash memory chip. As another example, an ALU may be assigned to a sub-block construct, such as to each bit line in the block. Having ALUs resident in the SSD enables more processing to be performed within the SSD and reduces the need to transmit data outside of the SSD for processing.
1. A solid state device (SSD) controller comprising:
an arithmetic logic unit (ALU);
wherein the SSD controller is configured to:
receive a write command from a host device, the write command comprising one or more values;
in response to receiving the write command, send a write instruction to one or more memory chips in communication with the SSD controller in order for the one or more memory chips to store the one or more values in memory within the one or more memory chips;
receive a command from the host device;
in response to receiving the command, send an instruction to the one or more memory chips, the instruction indicative to the one or more memory chips to use mathematical computation functionality or logic functionality on the one or more values previously stored in the memory in order to generate one or more results; and
receive from the one or more memory chips at least a part of the one or more results or an indication of the one or more results.
2. The SSD controller of claim 1 , wherein the SSD controller is configured to use the ALU to perform a first set of functions; and
wherein the instruction sent to the one or more memory chips is configured to instruct the one or more memory chips to use a second set of functions.
3. The SSD controller of claim 2 , wherein the first set of functions comprises higher-level functions; and
wherein the second set of functions comprises lower-level functions.
4. The SSD controller of claim 3 , wherein the SSD controller is further configured to:
review the command received from the host device;
determine one or more lower-level functions to perform responsive to the received command; and
determine which of the one or more memory chips to send an instruction to perform the determined one or more lower-level functions;
wherein the SSD controller is configured to send the instruction by sending to the determined one or more memory chips the instruction to perform the determined one or more lower-level functions on the one or more values stored in the memory.
5. The SSD controller of claim 3 , wherein the first set of functions comprise at least one of database functions, image processing functions, or file system functions.
6. The SSD controller of claim 1 , wherein the command from the host device comprises a search command;
wherein, responsive to receipt of the search command, the SSD controller is configured to send a search instruction to the one or more memory chips, the search instruction being indicative to the one or more memory chips to determine whether the one or more values stored in the memory match the data value in order to generate the one or more results responsive to the search command.
7. The SSD controller of claim 6 , wherein, responsive to receipt of the search command from the host device, the SSD controller is configured to determine one or more higher-level functions and one or more lower-level functions, at least one of the one or more lower-level functions comprises the search instruction;
wherein the one or more higher-level functions are different from the one or more lower-level functions;
wherein the SSD controller is further configured to perform the one or more higher-level functions; and
wherein the SSD controller is configured to command the one or more memory chips to perform the one or more lower-level functions.
8. The SSD controller of claim 1 , wherein, responsive to receipt, from the host device, of a mathematical computation command indicative to perform a mathematical computation, the SSD controller is configured to determine memory locations in the memory of a respective memory integrated circuit chip to perform the mathematical computation; and
wherein, responsive to determining the memory locations in the memory of a respective memory integrated circuit chip to perform the mathematical computation, the SSD controller is configured to send an indication of the mathematical computation to the respective memory integrated circuit chip.
9. The SSD controller of claim 8 , wherein the mathematical computation command comprises an image processing command.
10. The SSD controller of claim 1 , wherein the command comprises a file system command.
11. The SSD controller of claim 1 , wherein the command comprises an image processing command.
12. The SSD controller of claim 1 , further comprising an interface to communicate with the one or more memory chips.
13. A method for operating a solid state drive (SSD) controller, the SSD controller comprising an SSD controller arithmetic logic unit (ALU), the method comprising:
receiving, via an interface configured to communicate with a host device, a write command, the write command comprising one or more values;
responsive to receiving the write command, instructing a memory chip to store the one or more values in a memory of the memory chip;
receiving a command from the host device;
in response to receiving the command, sending an instruction to the memory chip, the instruction indicative to the memory chip to use mathematical computation functionality or logic functionality of the controller on the one or more values previously stored in the memory in order to generate one or more results; and
receiving from the memory chip at least a part of the one or more results or an indication of the one or more results.
14. The method of claim 13 , further comprising using, by the SSD controller, the ALU to perform a first set of functions; and
wherein the instruction sent to the memory chip is configured to instruct the memory chip to use a second set of functions.
15. The method of claim 14 , wherein the first set of functions comprises higher-level functions; and
wherein the second set of functions comprises lower-level functions.
16. The method of claim 15 , further comprising:
review the command received from the host device;
determine one or more lower-level functions to perform responsive to the received command; and
determine which memory chip to send an instruction to perform the determined one or more lower-level functions;
wherein sending the instruction comprises sending to the determined memory chip the instruction to perform the determined one or more lower-level functions on the one or more values stored in the memory.
17. The method of claim 15 , wherein the first set of functions comprise at least one of database functions, image processing functions, or file system functions.
18. The method of claim 13 , wherein the command from the host device comprises a search command;
wherein, responsive to receipt of the search command, sending a search instruction to the memory chip, the search instruction being indicative to the memory chip to determine whether the one or more values stored in the memory match the data value in order to generate the one or more results responsive to the search command.
19. The method of claim 18 , wherein, responsive to receipt of the search command from the host device, determining, by the SSD controller, one or more higher-level functions and one or more lower-level functions, at least one of the one or more lower-level functions comprises the search instruction;
wherein the one or more higher-level functions are different from the one or more lower-level functions;
further comprising performing the one or more higher-level functions; and
wherein the instruction is indicative to the memory chip to perform the one or more lower-level functions.
20. The method of claim 13 , wherein, responsive to receipt, from the host device, of a mathematical computation command indicative to perform a mathematical computation, determining memory locations in the memory of a respective memory chip to perform the mathematical computation, wherein the mathematical computation instruction is indicative to perform a mathematical computation; and
wherein, responsive to determining the memory locations in the memory of a respective memory chip to perform the mathematical computation, sending an indication of the mathematical computation to the respective memory chip.
21. The method of claim 20 , wherein the mathematical computation command comprises an image processing command.