Dual capacitor sense amplifier and methods therefor

1. A method for use with a memory array comprising a selected memory cell and a plurality of unselected memory cells, the selected memory cell coupled to a selected word line and a selected bit line, each unselected memory cell coupled to the selected bit line and a corresponding one of a plurality of unselected word lines, the selected bit line biased at a selected bit line voltage, each unselected word line biased at an unselected word line voltage, the method comprising:

integrating a first selected bit line current on a first capacitor of a sense amplifier for a first sense interval, the first selected bit line current comprising a first noise current of the memory array; and

integrating a second selected bit line current on a second capacitor of the sense amplifier for a second sense interval, the second selected bit line current comprising a sum of a current conducted by the selected memory cell and a second noise current of the memory array.

2. The method of claim 1 , wherein the first capacitor has a first capacitor value and the second capacitor has a second capacitor value, and the first capacitor value and the second capacitor value are equal within a predetermined capacitor matching accuracy.

3. The method of claim 1 , wherein the first noise current comprises an estimate of the second noise current.

4. The method of claim 1 , wherein the first sense interval substantially equals the second sense interval.

5. The method of claim 1 , wherein the selected memory cell and the unselected memory cells each comprise a reversible resistance-switching element.

6. A sense amplifier for use with a memory array comprising a selected memory cell and a plurality of unselected memory cells, the selected memory cell coupled to a selected word line and a selected bit line, each unselected memory cell coupled to the selected bit line and a corresponding one of a plurality of unselected word lines, the selected bit line biased at a selected bit line voltage, each unselected word line biased at an unselected word line voltage, the sense amplifier comprising:

an input terminal coupled to the selected bit line, an output terminal, a reference terminal and a clock terminal;

a comparator comprising a first input terminal, a second input terminal, and an output terminal coupled to the output terminal of the sense amplifier;

a first capacitor comprising a first terminal coupled to the input terminal of the sense amplifier and the first input terminal of the comparator, and a second terminal coupled to the clock terminal; and

a second capacitor comprising a first terminal coupled to the input terminal of the sense amplifier and the second input terminal of the comparator, and a second terminal coupled to the reference terminal.

7. The sense amplifier of claim 6 , wherein the first capacitor has a first capacitor value and the second capacitor has a second capacitor value, and the first capacitor value and the second capacitor value are equal within a predetermined capacitor matching accuracy.

8. The sense amplifier of claim 6 , further comprising:

a first switch coupled between the first terminal of the first capacitor and the input terminal of the sense amplifier; and

a second switch coupled between the first terminal of the second capacitor and the input terminal of the sense amplifier.

9. The sense amplifier of claim 8 , wherein:

the first switch connects the first terminal of the first capacitor and the input terminal of the sense amplifier for a first sense interval; and

the second switch connects the first terminal of the second capacitor and the input terminal of the sense amplifier for a second sense interval,

wherein the first sense interval substantially equals the second sense interval.

10. The sense amplifier of claim 6 , further comprising:

a pre-charge input terminal; and

a third switch coupled between the pre-charge input terminal and the first terminal of the first capacitor and the first terminal of the second capacitor.

11. The sense amplifier of claim 6 , further comprising a fourth switch coupled between the clock terminal and the second terminal of the first capacitor and the second terminal of the second capacitor.

12. The sense amplifier of claim 6 , further comprising a fifth switch coupled between the second terminal of the second capacitor and the reference terminal.

13. A method for determining a data value of a selected memory cell of a memory array, the selected memory cell coupled to a selected word line and a selected bit line, the memory array further comprising a plurality of unselected memory cells, each unselected memory cell coupled to the selected bit line and a corresponding one of a plurality of unselected word lines, the selected bit line biased at a selected bit line voltage, each unselected word line biased at an unselected word line voltage, the method comprising:

providing a sense amplifier comprising a first capacitor, a second capacitor, a reference terminal coupled to a reference voltage, and an output terminal;

generating a first voltage on the first capacitor proportional to a first noise current in the memory array;

generating a second voltage on the second capacitor proportional to a current conducted by the selected memory cell;

generating a third voltage on the second capacitor proportional to a second noise current in the memory array;

generating an output voltage at the output terminal, wherein the output voltage is proportional to a difference between the reference voltage and the second voltage and a difference between the first voltage and the third voltage; and

determining the data value based on the output voltage.

14. The method of claim 13 , wherein the first capacitor has a first capacitor value and the second capacitor has a second capacitor value, and the first capacitor value and the second capacitor value are equal within a predetermined capacitor matching accuracy.

15. The method of claim 13 , wherein the first voltage substantially equals the third voltage.

16. The method of claim 13 , wherein generating the first voltage comprises:

biasing the selected word line to the unselected word line voltage; and

coupling the bit line to the first capacitor for a first sense interval.

17. The method of claim 13 , wherein generating a second voltage and generating a third voltage comprises:

biasing the selected word line to a selected word line voltage; and

coupling the bit line to the second capacitor for a second sense interval.

18. The method of claim 13 , wherein:

generating the first voltage comprises a first sense interval and generating the second voltage and generating a the third voltage comprises a second sense interval; and

the first sense interval substantially equals the second sense interval.

19. The method of claim 13 , wherein generating the output voltage comprises:

coupling a first terminal of the first capacitor to a first input terminal of a comparator, and coupling a second terminal of the first capacitor to a ground potential;

coupling a first terminal of the second capacitor to a second terminal of the comparator, and coupling a second terminal of the second capacitor to the reference terminal; and

coupling an output of the comparator to the output terminal of the sense amplifier.

20. The method of claim 13 , wherein the selected memory cell and the unselected memory cells each comprise a reversible resistance-switching element.

21. A method for use with a memory array comprising a selected memory cell and a plurality of unselected memory cells, the selected memory cell coupled to a selected word line and a selected bit line, each unselected memory cell coupled to the selected bit line and a corresponding one of a plurality of unselected word lines, the selected bit line biased at a selected bit line voltage, each unselected word line biased at an unselected word line voltage, the method comprising:

providing a sense amplifier comprising:

an input terminal coupled to the selected bit line, an output terminal, a reference terminal and a clock terminal;

a comparator comprising a first input terminal, a second input terminal, and an output terminal coupled to the output terminal of the sense amplifier;

a first capacitor comprising a first terminal coupled to the input terminal of the sense amplifier and the first terminal of the comparator, and a second terminal coupled to the clock terminal; and

a second capacitor comprising a first terminal coupled to the input terminal of the sense amplifier and the second terminal of the comparator, and a second terminal coupled to the reference terminal.