Large array of upward pointinig p-i-n diodes having large and uniform current

1. A circuit comprising:

a plurality of vertically oriented p-i-n diodes, wherein each p-i-n diode is coupled to a resistivity-switching element and comprises a bottom heavily doped p-type region,

wherein when a voltage between about 1.5 volts and about 3.0 volts is applied across each p-i-n diode, a current of at least 1.5 microamps flows through 99 percent of the p-i-n diodes.

2. The circuit of claim 1 , wherein when a voltage between about 1.8 volts and about 2.2 volts is applied across each p-i-n diode, a current of at least 1.5 microamps flows through 99 percent of the p-i-n diodes.

3. The circuit of claim 1 , wherein the resistivity-switching element comprises a binary metal oxide or a carbon nanotube fabric.

4. The memory of claim 1 , wherein the resistivity-switching element comprises one or more of Ni x O y , Nb x O y , Ti x O y , Hf x O y , Al x O y , Mg x O y , Co x O y , Cr x O y , V x O y , Zn x O y , Zr x O y , B x N y and Al x N y .

5. The circuit of claim 1 , wherein each p-i-n diode is in contact with a silicide, germanide, or silicide-germanide layer.

6. The circuit of claim 1 , further comprising:

a first plurality of substantially parallel, substantially coplanar rail-shaped conductors formed above a substrate; and

a second plurality of substantially parallel, substantially coplanar rail-shaped conductors formed above the first plurality of substantially parallel, substantially coplanar rail-shaped conductors,

wherein each p-i-n diode is vertically disposed between one of the first plurality of substantially parallel, substantially coplanar rail-shaped conductors and one of the second plurality of substantially parallel, substantially coplanar rail-shaped conductors.

7. The circuit of claim 1 , wherein the plurality of vertically oriented p-i-n diodes are formed above a substrate.

8. A monolithic three-dimensional circuit comprising:

a first circuit level comprising a plurality of vertically oriented p-i-n diodes, wherein each p-i-n diode is coupled to a resistivity-switching element and comprises a bottom heavily doped p-type region, and wherein when a voltage between about 1.5 volts and about 3.0 volts is applied across each p-i-n diode, a current of at least 1.5 microamps flows through 99 percent of the p-i-n diodes; and

a second circuit level monolithically formed above the first circuit level.

9. The monolithic three-dimensional circuit of claim 8 , wherein when a voltage between about 1.8 volts and about 2.2 volts is applied across each p-i-n diode, a current of at least 1.5 microamps flows through 99 percent of the p-i-n diodes.

10. The monolithic three-dimensional circuit of claim 8 , wherein the resistivity-switching element comprises a binary metal oxide or a carbon nanotube fabric.

11. The monolithic three-dimensional circuit of claim 8 , wherein the resistivity-switching element comprises one or more of Ni x O y , Nb x O y , Ti x O y , Hf x O y , Al x O y , Mg x O y ,Co x O y , Cr x O y , V x O y , Zn x O y , Zr x O y , B x N y and Al x N y .

12. The monolithic three-dimensional circuit of claim 8 , wherein each p-i-n diode is in contact with a silicide, germanide, or silicide-germanide layer.

13. The monolithic three-dimensional circuit of claim 8 , further comprising:

a first plurality of substantially parallel, substantially coplanar rail-shaped conductors formed above a substrate; and

a second plurality of substantially parallel, substantially coplanar rail-shaped conductors formed above the first plurality of substantially parallel, substantially coplanar rail-shaped conductors,

wherein each vertically oriented p-i-n diode in the first circuit level is vertically disposed between one of the first plurality of substantially parallel, substantially coplanar rail-shaped conductors and one of the second plurality of substantially parallel, substantially coplanar rail-shaped conductors.

14. A method comprising:

forming a plurality of vertically oriented p-i-n diodes, wherein each p-i-n diode is coupled to a resistivity-switching element and comprises a bottom heavily doped p-type region,

wherein when a voltage between about 1.5 volts and about 3.0 volts is applied across each p-i-n diode, a current of at least 1.5 microamps flows through 99 percent of the p-i-n diodes.

15. The method of claim 14 , wherein when a voltage between about 1.8 volts and about 2.2 volts is applied across each p-i-n diode, a current of at least 1.5 microamps flows through 99 percent of the p-i-n diodes.

16. The method of claim 14 , wherein the resistivity-switching element comprises a binary metal oxide or a carbon nanotube fabric.

17. The method of claim 14 , wherein the resistivity-switching element comprises one or more of Ni x O y , Nb x O y , Ti x O y , Hf x O y , Al x O y , Mg x O y , Co x O y , Cr x O y , V x O y , Zn x O y , Zr x O y , B x N y and Al x N y .

18. The method of claim 14 , further comprising forming each p-i-n diode in contact with a silicide, germanide, or silicide-germanide layer.

19. The method of claim 14 , further comprising:

forming a first plurality of substantially parallel, substantially coplanar rail-shaped conductors formed above a substrate; and

forming a second plurality of substantially parallel, substantially coplanar rail-shaped conductors formed above the first plurality of substantially parallel, substantially coplanar rail-shaped conductors,

vertically disposing each p-i-n diode between one of the first plurality of substantially parallel, substantially coplanar rail-shaped conductors and one of the second plurality of substantially parallel, substantially coplanar rail-shaped conductors.