Patent Assignment
Reel/Frame 038807/0898
CHANGE OF NAME
Recorded: 2016-05-25
Received: 2016-05-25
Pages: 17
Assignor
SANDISK TECHNOLOGIES INC
Executed: 2016-05-16
Assignee
SANDISK TECHNOLOGIES LLC
6900 DALLAS PARKWAY, SUITE 325, PLANO, TX, 75024, UNITED STATES
Covered Applications
(100)
Biasing for Wear Leveling in Storage Systems
App. No. 14/137,440
→
Multiprocessor Storage Controller
App. No. 13/894,326
→
FIRMWARE UPDATES FOR MULTIPLE PRODUCT CONFIGURATIONS
App. No. 13/894,206
→
Flash Storage Controller Execute Loop
App. No. 13/892,214
→
METHODS AND APPARATUS FOR REDUCING PROGRAMMING TIME OF A MEMORY CELL
App. No. 13/890,622
→
METHODS FOR PROTECTING PATTERNED FEATURES DURING TRENCH ETCH
App. No. 13/890,321
→
Providing Reliability Metrics For Decoding Data In Non-Volatile Storage
App. No. 13/888,145
→
BIT LINE BL ISOLATION SCHEME DURING ERASE OPERATION FOR NON-VOLATILE STORAGE
App. No. 13/886,852
→
THREE DIMENSIONAL NON-VOLATILE STORAGE WITH INTERLEAVED VERTICAL SELECT DEVICES ABOVE AND BELOW VERTICAL BIT LINES
App. No. 13/886,874
→
FLASH STORAGE CONTROLLER EXECUTE LOOP
App. No. 13/887,018
→
Sigma Delta Over-Sampling Charge Pump Analog-To-Digital Converter
App. No. 13/886,066
→
METHOD OF MAKING ULTRAHIGH DENSITY VERTICAL NAND MEMORY DEVICE
App. No. 13/875,854
→
DEFECTIVE BLOCK MANAGEMENT
App. No. 13/871,528
→
MEMORY CELL THAT INCLUDES A SIDEWALL COLLAR FOR PILLAR ISOLATION AND METHODS OF FORMING THE SAME
App. No. 13/868,667
→
High Speed Signaling Techniques to Improve Performance of Integrated Circuits
App. No. 13/867,259
→
MEMORY CELL FLOATING GATE REPLACEMENT
App. No. 13/865,865
→
LARGE ARRAY OF UPWARD POINTING P-I-N DIODES HAVING LARGE AND UNIFORM CURRENT
App. No. 13/863,027
→
METHOD OF INHIBITING WIRE COLLAPSE
App. No. 13/862,222
→
NON-VOLATILE STORAGE HAVING A CONNECTED SOURCE AND WELL
App. No. 13/861,613
→
SYSTEMS AND METHODS TO UPDATE REFERENCE VOLTAGES OF NON-VOLATILE MEMORY
App. No. 13/860,777
→
SEQUENTIAL PROGRAMMING OF SETS OF NON-VOLATILE ELEMENTS TO IMPROVE BOOST VOLTAGE CLAMPING
App. No. 13/860,141
→
STORAGE CONTROL SYSTEM WITH POWER DOWN MECHANISM AND METHOD OF OPERATION THEREOF
App. No. 13/855,567
→
HIGH ENDURANCE NONVOLATILE MEMORY
App. No. 13/855,579
→
ELECTRONIC SYSTEM WITH SYSTEM MODIFICATION CONTROL MECHANISM AND METHOD OF OPERATION THEREOF
App. No. 13/851,928
→
NON-VOLATILE STORAGE WITH METAL OXIDE SWITCHING ELEMENT AND METHODS FOR FABRICATING THE SAME
App. No. 13/848,603
→
PERIODIC ERASE OPERATION FOR A NON-VOLATILE MEDIUM
App. No. 13/837,818
→
WRITE ADMITTANCE POLICY FOR A MEMORY CACHE
App. No. 13/832,843
→
APPARATUS, SYSTEM, AND METHOD FOR WEAR MANAGEMENT
App. No. 13/844,338
→
CONNECTOR OF A UNIVERSAL SERIAL BUS DEVICE
App. No. 13/841,934
→
FLASH MEMORY TECHNIQUES FOR RECOVERING FROM WRITE INTERRUPT RESULTING FROM VOLTAGE FAULT
App. No. 13/841,180
→
SYSTEM AND METHOD TO REDUCE READ LATENCY OF A DATA STORAGE DEVICE
App. No. 13/838,662
→
Systems, Methods, and Devices for Multi-Dimensional Flash RAID Data Protection
App. No. 13/831,707
→
Program Cycle Skip Evaluation Before Write Operations In Non-Volatile Memory
App. No. 13/839,366
→
COMPRESSING DATA FROM MULTIPLE READS FOR ERROR CONTROL MANAGEMENT IN MEMORY SYSTEMS
App. No. 13/831,686
→
TRAP PASSIVATION IN MEMORY CELL WITH METAL OXIDE SWITCHING ELEMENT
App. No. 13/837,917
→
Apparatus, System, and Method for Accessing Memory
App. No. 13/836,826
→
Dynamic Address Grouping For Parallel Programming In Non-Volatile Memory
App. No. 13/839,300
→
PROGRAM SUSPEND/RESUME FOR MEMORY
App. No. 13/834,955
→
Adaptive LLR Based on Syndrome Weight
App. No. 13/831,713
→
Auto-Commit Memory
App. No. 13/838,070
→
SYSTEM AND METHOD OF DETERMINING READING VOLTAGES OF A DATA STORAGE DEVICE
App. No. 13/839,430
→
METHOD FOR FORMING STAIRCASE WORD LINES IN A 3D NON-VOLATILE MEMORY HAVING VERTICAL BIT LINES
App. No. 13/840,201
→
NON-VOLATILE MEMORY HAVING 3D ARRAY ARCHITECTURE WITH STAIRCASE WORD LINES AND VERTICAL BIT LINES AND METHODS THEREOF
App. No. 13/840,759
→
MANAGING DATA RELIABILITY
App. No. 13/836,620
→
3D MEMORY WITH VERTICAL BIT LINES AND STAIRCASE WORD LINES AND VERTICAL SWITCHES AND METHODS THEREOF
App. No. 13/835,032
→
EPOCH BASED STORAGE MANAGEMENT FOR A STORAGE DEVICE
App. No. 13/831,448
→
ESTIMATING ACCESS FREQUENCY STATISTICS FOR STORAGE DEVICE
App. No. 13/831,475
→
DATA SEARCH USING BLOOM FILTERS AND NAND BASED CONTENT ADDRESSABLE MEMORY
App. No. 13/827,609
→
SYSTEM, METHOD AND APPARATUS FOR HANDLING POWER LIMIT RESTRICTIONS IN FLASH MEMORY DEVICES
App. No. 13/829,426
→
System and Method for Selectively Routing Cached Objects
App. No. 13/803,721
→
SEMICONDUCTOR DEVICE WITH DIE STACK ARRANGEMENT INCLUDING STAGGERED DIE AND EFFICIENT WIRE BONDING
App. No. 13/829,739
→
MEMORY SYSTEM HAVING AN UNEQUAL NUMBER OF MEMORY DIE ON DIFFERENT CONTROL CHANNELS
App. No. 13/827,499
→
PRESERVING DATA FROM ADJACENT WORD LINES WHILE PROGRAMMING BINARY NON-VOLATILE STORAGE ELEMENTS
App. No. 13/831,420
→
METHOD AND SYSTEM FOR MANAGING PROGRAM CYCLES INCLUDING MAINTENANCE PROGRAMMING OPERATIONS IN A MULTI-LAYER MEMORY
App. No. 13/826,738
→
DIGITAL SOFT START WITH CONTINUOUS RAMP-UP
App. No. 13/827,601
→
IMMUNITY AGAINST TEMPORARY AND SHORT POWER DROPS IN NON-VOLATILE MEMORY
App. No. 13/803,835
→
METHOD AND SYSTEM FOR MANAGING BLOCK RECLAIM OPERATIONS IN A MULTI-LAYER MEMORY
App. No. 13/826,944
→
Compensation For Temperature Dependence Of Bit Line Resistance
App. No. 13/828,361
→
METHOD AND SYSTEM FOR PROGRAM SCHEDULING IN A MULTI-LAYER MEMORY
App. No. 13/827,204
→
Immunity Against Temporary and Short Power Drops in Non-Volatile Memory: Pausing Techninques
App. No. 13/803,882
→
MANAGING CONFIGURATION PARAMETERS FOR A NON-VOLATILE MEDIUM
App. No. 13/830,989
→
ARCHITECTURES FOR DATA ANALYTICS USING COMPUTATIONAL NAND MEMORY
App. No. 13/827,407
→
SYSTEMS AND METHODS TO AVOID FALSE VERIFY AND FALSE READ
App. No. 13/801,655
→
ACTIVE PROBE ADAPTOR
App. No. 13/801,956
→
Select Transistor Tuning
App. No. 13/801,800
→
WEIGHTED READ SCRUB FOR NONVOLATILE MEMORY
App. No. 13/801,741
→
TRACKING ERASE PULSES FOR NON-VOLATILE MEMORY
App. No. 13/800,430
→
ERASE SUSPEND/RESUME FOR MEMORY
App. No. 13/800,628
→
NONVOLATILE MEMORY AND METHOD WITH IMPROVED I/O INTERFACE
App. No. 13/801,142
→
TRACKING ERASE OPERATIONS TO REGIONS OF NON-VOLATILE MEMORY
App. No. 13/800,224
→
TRACKING CELL ERASE COUNTS OF NON-VOLATILE MEMORY
App. No. 13/800,637
→
Systems and Methods for Performing Defect Detection and Data Recovery in a Memory System
App. No. 13/795,460
→
DETECTING EFFECT OF CORRUPTING EVENT ON PRELOADED DATA IN NON-VOLATILE MEMORY
App. No. 13/796,841
→
SHARED BIT LINE STRING ARCHITECTURE
App. No. 13/797,298
→
BAD COLUMN HANDLING IN FLASH MEMORY
App. No. 13/793,282
→
NON-VOLATILE STORAGE WITH SHARED BIT LINES AND FLAT MEMORY CELLS
App. No. 13/793,925
→
DE-DUPLICATION SYSTEM USING NAND FLASH BASED CONTENT ADDRESSABLE MEMORY
App. No. 13/794,428
→
A METHOD AND NON-VOLATILE MEMORY DEVICE FOR IMPROVING LATENCY TOGETHER WITH WRITE PROTECTION
App. No. 13/793,209
→
DE-DUPLICATION TECHNIQUES USING NAND FLASH BASED CONTENT ADDRESSABLE MEMORY
App. No. 13/794,398
→
NON-VOLATILE MEMORY HAVING 3D ARRAY ARCHITECTURE WITH BIT LINE VOLTAGE CONTROL AND METHODS THEREOF
App. No. 13/794,344
→
Nanodot-Enhanced Hybrid Floating Gate for Non-Volatile Memory Devices
App. No. 13/792,662
→
Flash Memory Using Virtual Physical Addresses
App. No. 13/793,581
→
Optimized Configurable NAND Parameters
App. No. 13/791,200
→
Defect Or Program Disturb Detection With Full Data Recovery Capability
App. No. 13/790,469
→
Enhanced Dynamic Read Process with Single-Level Cell Segmentation
App. No. 13/789,536
→
HYBRID NON-VOLATILE MEMORY CELLS FOR SHARED BIT LINE
App. No. 13/788,183
→
MEMORIES WITH CYLINDRICAL READ/WRITE STACKS
App. No. 13/789,375
→
CONNECTOR DEVICE
App. No. 13/789,033
→
VERTICAL BIT LINE TFT DECODER FOR HIGH VOLTAGE OPERATION
App. No. 13/788,990
→
Compensation Scheme to Improve the Stability of the Operational Amplifiers
App. No. 13/787,419
→
INTERNAL DATA LOAD FOR NON-VOLATILE STORAGE
App. No. 13/786,190
→
Peak Current Management in Multi-Die Non-Volatile Memory Devices
App. No. 13/785,720
→
NON-VOLATILE STORAGE WITH PROCESS THAT REDUCES READ DISTURB ON END WORDLINES
App. No. 13/783,928
→
MEMORY CELLS HAVING STORAGE ELEMENTS THAT SHARE MATERIAL LAYERS WITH STEERING ELEMENTS AND METHODS OF FORMING THE SAME
App. No. 13/783,585
→
NON-VOLATILE STORAGE WITH READ PROCESS THAT REDUCES DISTURB
App. No. 13/783,781
→
Erased Page Confirmation in Multilevel Memory
App. No. 13/784,693
→
METHOD OF FABRICATING A SELF-ALIGNING DAMASCENE MEMORY STRUCTURE
App. No. 13/781,983
→
Erased State Reading
App. No. 13/783,068
→
Auto-Calibration for High Speed Input/Output
App. No. 13/780,676
→
RERAM FORMING WITH RESET AND ILOAD COMPENSATION
App. No. 13/781,503
→