Granted Patent B2

US 9,223,514 · App. 13/800,628 · Granted Dec 29, 2015

Abstract

Claims (67)

1. An apparatus comprising:

an input/output (I/O) interface configured to couple a controller to an I/O buffer of a memory device;

an erase module coupled to the I/O interface, wherein the erase module is configured to issue an instruction to the memory device to erase data from the memory device; and

an erase suspend module coupled to the I/O interface, the erase suspend module configured to determine that an erase operation executing within the memory device satisfies a suspend policy in response to receiving a memory access request to perform an operation on the memory device on which the erase operation is executing and to issue a suspend command to the memory device to suspend the erase operation, the suspend policy comprising one or more of suspending the erase operation in response to determining that the erase operation is less than halfway completed, suspending the erase operation up to a maximum number of times for suspending a single erase operation, and suspending the erase operation based on an expected rate of memory access requests to the memory device.

2. The apparatus of claim 1 , wherein the suspend policy comprises suspending the erase operation automatically in response to receiving the memory access request.

3. The apparatus of claim 1 , wherein the suspend policy comprises suspending the erase operation in response to determining that the erase operation is less than halfway completed.

4. The apparatus of claim 1 , wherein the suspend policy comprises suspending the erase operation up to a maximum number of times for suspending a single erase operation.

5. The apparatus of claim 1 , wherein the suspend policy comprises suspending the erase operation in response to determining that a benefit associated with suspending the erase operation is greater than a predetermined erase penalty value, wherein the benefit is based on a remaining erase time.

6. The apparatus of claim 1 , wherein the suspend policy comprises suspending the erase operation based on an expected rate of memory access requests to the memory device.

7. The apparatus of claim 1 , wherein the suspend policy comprises:

increasing a probability of suspending the erase operation for each memory access request in a queue of access requests; and

decreasing the probability as the erase operation nears completion.

8. The apparatus of claim 1 , wherein the erase suspend module is further configured to:

store an erase step associated with the erase operation in response to suspending the erase operation; and

resume the erase operation at the erase step in response to completing an operation associated with the memory access request.

9. A method for suspending an erase operation at a memory device, the method comprising:

performing a portion of an erase operation comprising erasing data from a plurality of memory elements in a memory array of the memory device;

receiving a memory access request to the memory device;

calculating a suspend threshold based on a predefined suspend policy determined for the memory device, the suspend policy comprising suspending the erase operation based on an expected rate of memory access requests to the memory device;

determining that the erase operation meets the suspend threshold; and

suspending the erase operation.

10. The method of claim 9 , wherein the suspend policy comprises suspending the erase operation automatically in response to receiving the memory access request.

11. The method of claim 9 , wherein the suspend policy comprises suspending the erase operation in response to determining that the erase operation is less than halfway completed.

12. The method of claim 9 , wherein the suspend policy comprises a maximum number of times for suspending a single erase operation.

13. The method of claim 9 , wherein the suspend policy comprises suspending the erase operation in response to determining that a benefit associated with suspending the erase operation is greater than a predetermined erase penalty value, wherein the benefit is based on a remaining erase time.

14. The method of claim 9 , wherein the suspend policy comprises:

increasing a probability of suspending the erase operation for each memory access request in a queue of access requests; and

decreasing the probability as the erase operation nears completion.

15. The method of claim 9 , further comprising:

storing an erase step associated with the erase operation in response to suspending the erase operation; and

resuming the erase operation at the erase step in response to completing an operation associated with the memory access request.

16. A memory device comprising:

a memory array with a plurality of memory elements, wherein each memory element is configured to store data;

a memory control manager coupled to the memory array and to an input/output (I/O) interface of a memory device controller, wherein the memory control manager is configured to:

determine that an erase operation executing within the memory device satisfies a suspend policy in response to receiving a memory access request from the I/O interface, the suspend policy comprising pausing the erase operation based on the erase operation being less than halfway completed; and

pause the erase operation.

17. The device of claim 16 , wherein the suspend policy comprises pausing the erase operation automatically in response to receiving the memory access request.

18. The device of claim 16 , wherein the suspend policy comprises pausing the erase operation up to a maximum number of times for suspending a single erase operation.

19. The device of claim 16 , wherein the suspend policy comprises pausing the erase operation in response to determining that a benefit associated with suspending the erase operation is greater than a predetermined erase penalty value, wherein the benefit is based on a remaining erase time.

20. The device of claim 16 , wherein the suspend policy comprises:

increasing a probability of pausing the erase operation for each read/write signal in a queue of command signals; and

decreasing the probability as the erase operation nears completion.

21. The device of claim 16 , further comprising an erase register configured to store an erase step associated with the erase operation in response to pausing the erase operation, wherein the memory control manager is further configured to resume the erase operation at the erase step in response to completing an operation associated with the memory access request.

22. A system comprising:

a memory device comprising a plurality of memory elements;

means for storing data on the plurality of memory elements of the memory device;

means for erasing data from the memory elements;

means for determining that an erase operation executing within the memory device satisfies a suspend policy in response to receiving a memory access request, the suspend policy comprising suspending the erase operation up to a maximum number of times for suspending a single erase operation; and

means for suspending the erase operation.

23. The system of claim 22 , further comprising:

means for storing an erase step associated with the erase operation in response to suspending the erase operation; and

means for resuming the erase operation at the erase step in response to completing a read/write operation associated with a read/write signal.

24. A memory device, comprising:

a memory array with a plurality of memory elements, wherein each memory element is configured to store data;

a memory control manager configured to be coupled to the memory array and to an input/output (I/O) interface of a memory device controller, wherein the memory control manager is configured to:

calculate a suspend threshold based on a suspend policy that comprises counts per erase block of the memory device of a number of times an erase block has been programmed and erased;

determine that an erase operation executing within the memory device meets the suspend threshold in response to receiving a memory access request from the I/O interface; and

pause the erase operation.

25. The memory device of claim 24 , wherein the suspend policy further comprises decreasing a probability of suspending the erase operation as the erase operation nears completion.

26. The memory device of claim 24 , wherein the suspend policy is based on the application accessing the memory device.

27. An apparatus comprising:

a memory controller, the memory controller comprising,

an input/output (I/O) interface configured to couple the memory controller to an I/O buffer of a memory device;

wherein the memory controller is configured to determine, in response to receiving a request to perform another operation on the memory device on which the erase operation is executing, whether an erase operation executing on the memory device satisfies a suspend policy; and

wherein the memory controller is configured to issue a suspend command to the memory device to suspend the erase operation in response to determining that the erase operation satisfies the suspend policy, the suspend policy comprising one or more of suspending the erase operation in response to determining that the erase operation is less than halfway completed, suspending the erase operation up to a maximum number of times for suspending a single erase operation, and suspending the erase operation based on an expected rate of memory access requests to the memory device.

28. The apparatus of claim 27 , wherein the suspend policy comprises suspending the erase operation up to a maximum number of times for suspending a single erase operation.

29. The apparatus of claim 27 , wherein the suspend policy comprises suspending the erase operation based on an expected rate of memory access requests to the memory device.

Assignments (9)