3D memory with vertical bit lines and staircase word lines and vertical switches and methods thereof
A 3D memory with vertical local bit lines global bit lines has an in-line vertical switch in the form of a thin film transistor (TFT) formed as a vertical structure, to switch a local bit line to a global bit line. The TFT is implemented to switch a maximum of current carried by the local bit line by a strongly coupled select gate which must be fitted within the space around the local bit line. Maximum thickness of the select gate is implemented with the select gate exclusively occupying the space along the x-direction from both sides of the local bit line. The switches for odd and even bit lines of the row are staggered and offset in the z-direction so that the select gates of even and odd local bit lines are not coincident along the x-direction. The switching is further enhanced with a wrap-around select gate.
1. A non-volatile memory, comprising:
memory elements arranged in a three-dimensional pattern defined by rectangular coordinates having x, y and z-directions and with a plurality of parallel planes from a bottom plane to a top plane stacked in the z-direction over a semiconductor substrate;
a plurality of local bit lines elongated in the z-direction through the plurality of parallel planes and arranged in a two-dimensional rectangular array of bit line pillars having rows in the x-direction and columns in the y-direction;
a plurality of global bit lines elongated in the y-direction; and
a vertical switch in line with each local bit line along the z-direction to switch one end of the local bit line to a corresponding global bit line, said vertical switch being a thin film transistor with a transistor junction in the z-direction in line with the local bit line and having a select gate, the select gate being insulated from said plurality of local bit lines and having a thickness extending along the x-direction between the local bit line and adjacent local bit lines on each side of the local bit line.
2. The non-volatile memory as in claim 1 , wherein:
a row of local bit lines has a corresponding row of thin film transistors; and thin film transistors of an even row of local bit lines are offset in the z-direction from thin film transistors of an odd row of local bit lines so that the select gates of even and odd rows of local bit lines are not coincident.
3. The non-volatile memory as in claim 1 , further comprising:
a gate oxide between each transistor junction and the respective select gate.
4. The non-volatile memory as in claim 1 , further comprising:
a gate oxide between each select gate and a local bit line adjacent to the local bit line.
5. The non-volatile memory as in claim 1 , wherein:
the select gates on each side of the local bit line are electrically connected.
6. The non-volatile memory as in claim 1 , wherein:
a row of local bit lines have corresponding select gates electrically connected to form a row select line for said row of local bit lines.
7. The non-volatile memory as in claim 1 , wherein:
the local bit line is formed from N-doped polysilicon; and
the thin film transistor is incorporated as an end portion of the local bit line formed into an in-line NPN transistor junction.
8. The non-volatile memory as in claim 1 , wherein:
the select gate of each thin film transistor surrounds and wraps around all sides of the thin film transistor junction in a plane defined by the x-direction and y-direction.
9. The non-volatile memory as in claim 1 , wherein:
the vertical switch switches a bottom end of the local bit line to a corresponding global bit line below the bottom plane.
10. The non-volatile memory as in claim 1 , wherein:
the vertical switch switches a top end of the local bit line to a corresponding global bit line above the top plane.
11. The non-volatile memory as in claim 1 , wherein:
the even vertical switch is located near a first end of a local bit line in an even row along the x-direction and switches the first end of the local bit line in the even row to a corresponding global bit line from a first surface of the plurality of planes and the odd vertical switch is located near the second end of a local bit line in an odd row along the x-direction and switches the second end of the local bit line in the odd row to a corresponding global bit line from a second surface of the plurality of planes opposite the first surface.
12. A method of operating a non-volatile memory, comprising:
providing memory elements arranged in a three-dimensional pattern defined by rectangular coordinates having x, y and z-directions and with a plurality of parallel planes from a bottom plane to a top plane stacked in the z-direction over a semiconductor substrate;
providing a plurality of local bit lines elongated in the z-direction through the plurality of parallel planes and arranged in a two-dimensional rectangular array of bit line pillars having rows in the x-direction and columns in the y-direction;
providing a plurality of global bit lines elongated in the y-direction;
providing a vertical switch in the z-direction in line with each local bit line along the z-direction to switch one end of the local bit line to a corresponding global bit line, said vertical switch being a thin film transistor with a transistor junction in line with the local bit line and having a select gate, the select gate being insulated from said plurality of local bit line and having a thickness extending along the x-direction between the local bit line and adjacent local bit lines on each side of the local bit line; and
switching a row of local bit lines to corresponding global bit lines by applying a select signal to the respective select gates of the row of local bit lines.
13. The method as in claim 12 , wherein:
a row of local bit lines has a corresponding row of thin film transistors; and thin film transistors of an even row of local bit lines are offset in the z-direction from thin film transistors of an odd row of local bit lines so that the select gates of even and odd rows of local bit lines are not coincident.
14. The method as in claim 12 , further comprising:
providing a gate oxide between each transistor junction and the respective select gate.
15. The method as in claim 12 , further comprising:
providing a gate oxide between each select gate and a local bit line adjacent to the local bit line.
16. The method as in claim 12 , wherein:
the select gates on each side of the local bit line are electrically connected.
17. The method as in claim 12 , wherein:
a row of local bit lines have corresponding select gates electrically connected to form a row select line for said row of local bit lines.
18. The method as in claim 12 , wherein:
the local bit line is formed from N-doped polysilicon; and
the thin film transistor is incorporated as an end portion of the local bit line formed into an in-line NPN transistor junction.
19. The method as in claim 12 , wherein:
the select gate of each thin film transistor surrounds and wraps around all sides of the thin film transistor junction in a plane defined by the x-direction and y-direction.
20. The method as in claim 12 , wherein:
the vertical switch switches a bottom end of the local bit line to a corresponding global bit line below the bottom plane.
21. The method as in claim 12 , wherein:
the vertical switch switches a top end of the local bit line to a corresponding global bit line above the top plane.
22. The method as in claim 12 , wherein:
the even vertical switch is located near a first end of a local bit line in an even row along the x-direction and switches the first end of the local bit line in the even row to a corresponding global bit line from a first surface of the plurality of planes and the odd vertical switch is located near the second end of a local bit line in an odd row along the x-direction and switches the second end of the local bit line in the odd row to a corresponding global bit line from a second surface of the plurality of planes opposite the first surface.