Methods and apparatus for reducing programming time of a memory cell
View Patent ↗A method is provided for programming a memory cell having a first terminal coupled to a word line and a second terminal coupled to a bit line. During a first predetermined time interval, the word line is switched from a first standby voltage to a first voltage, the bit line is switched from a second standby voltage to a predetermined voltage, and a voltage drop across the first and second terminals is a safe voltage that does not program the memory cell. During a second predetermined time interval, the word line is switched from the first voltage to a second voltage, and a voltage drop across the first and second terminals is a programming voltage that is sufficient to program the memory cell. Numerous other aspects are provided.
1. A method of programming a memory cell having a first terminal coupled to a word line and a second terminal coupled to a bit line, the method comprising:
during a first predetermined time interval, switching the word line from a first standby voltage to a first voltage, and switching the bit line from a second standby voltage to a predetermined voltage; and
during a second predetermined time interval, switching the word line from the first voltage to a second voltage,
wherein:
during the first predetermined time interval, a voltage drop across the first and second terminals is a safe voltage that does not program the memory cell, and
during the second predetermined time interval, a voltage drop across the first and second terminals is a programming voltage that is sufficient to program the memory cell.
2. The method of claim 1 , wherein a difference between the safe voltage and the programming voltage maximizes programming speed.
3. The method of claim 1 , wherein a difference between the safe voltage and the programming voltage distinguishes between programming and not programming the memory cell.
4. The method of claim 1 , wherein the bit line is switched to the predetermined voltage without limiting current.
5. The method of claim 1 , wherein the first voltage is higher than the second voltage.
6. The method of claim 1 , wherein switching the word line from the first voltage to a second voltage includes a VT drop.
7. Apparatus for programming a memory cell having a first terminal coupled to a word line and a second terminal coupled to a bit line, the apparatus comprising:
a control circuit coupled to the word line; and
a sense amplifier coupled to the bit line;
wherein:
during a first predetermined time interval, the control circuit is adapted to switch the word line from a first standby voltage to a first voltage, the sense amplifier is adapted to charge the bit line from a second standby voltage to a predetermined voltage, and a voltage drop across the first and second terminals is a safe voltage that does not program the memory cell, and
during a second predetermined time interval, the control circuit is adapted to switch the word line from the first voltage to a second voltage, and a voltage drop across the first and second terminals is a programming voltage that is sufficient to program the memory cell.
8. The apparatus of claim 7 , wherein the control circuit comprises a MUX or a diode-connected NMOS transistor and a bypass path.
9. The apparatus of claim 7 , wherein a difference between the safe voltage and the programming voltage maximizes programming speed.
10. The apparatus of claim 7 , wherein a difference between the safe voltage and the programming voltage distinguishes between programming and not programming the memory cell.
11. The apparatus of claim 7 , wherein the bit line is switched to the predetermined voltage without limiting current.
12. The apparatus of claim 7 , wherein the first voltage is higher than the second voltage.
13. The apparatus of claim 7 , wherein switching the word line from the first voltage to a second voltage includes a VT drop.
14. A memory array including a memory cell having a first terminal coupled to a word line and a second terminal coupled to a bit line, the memory array comprising:
a control circuit coupled to the word line; and
a sense amplifier coupled to the bit line;
wherein:
during a first predetermined time interval, the control circuit is adapted to switch the word line from a first standby voltage to a first voltage, the sense amplifier is adapted to charge the bit line from a second standby voltage to a predetermined voltage, and a voltage drop across the first and second terminals is a safe voltage that does not program the memory cell, and
during a second predetermined time interval, the control circuit is adapted to switch the word line from the first voltage to a second voltage, and a voltage drop across the first and second terminals is a programming voltage that is sufficient to program the memory cell.
15. The memory array of claim 14 , wherein the control circuit comprises MUX or a diode-connected NMOS transistor and a bypass path.
16. The memory array of claim 14 , wherein a difference between the safe voltage and the programming voltage maximizes programming speed.
17. The memory array of claim 14 , wherein a difference between the safe voltage and the programming voltage distinguishes between programming and not programming the memory cell.
18. The memory array of claim 14 , wherein the bit line is switched to the predetermined voltage without limiting current.
19. The memory array of claim 14 , wherein the first voltage is higher than the second voltage.
20. The memory array of claim 14 , wherein switching the word line from the first voltage to a second voltage includes a VT drop.