Multiple layer forming scheme for vertical cross point reram
Methods for forming non-volatile storage elements in a non-volatile storage system are described. In some embodiments, during a forming operation, a cross-point memory array may be biased such that waste currents are minimized or eliminated. In one example, the memory array may be biased such that a first word line comb is set to a first voltage, a second word line comb interdigitated with the first word line comb is set to the first voltage, and selected vertical bit lines are set to a second voltage such that a forming voltage is applied across non-volatile storage elements to be formed. In some embodiments, a memory array may include a plurality of word line comb layers and a forming operation may be concurrently performed on non-volatile storage elements on all of the plurality of word line comb layers or a subset of the plurality of word line comb layers.
1. A non-volatile storage system, comprising:
a memory array, the memory array includes a first group of vertical bit lines connected to a plurality of word line combs, the first group of vertical bit lines includes a first bit line, each word line comb of the plurality of word line combs is connected to the first bit line, the memory array includes a second group of vertical bit lines connected to the plurality of word line combs, the second group of vertical bit lines includes a second bit line, each word line comb of the plurality of word line combs is connected to the second bit line; and
one or more control circuits in communication with the memory array, the one or more control circuits cause a first forming operation to be performed to a first set of non-volatile storage elements connected to the first group of vertical bit lines and the plurality of word line combs, the one or more control circuits cause a second forming operation to be performed to a second set of non-volatile storage elements connected to the second group of vertical bit lines and the plurality of word line combs, the second forming operation is performed subsequent to the first forming operation, the first forming operation includes setting a first word line comb of the plurality of word line combs to a first voltage and setting a second word line comb of the plurality of word line combs to the first voltage, the first word line comb includes a first finger, the second word line comb includes a second finger, the first forming operation includes setting a first vertical bit line of the first group of vertical bit lines to a second voltage less than the first voltage, the first vertical bit line is connected to the first finger via a first storage element and is connected to the second finger via a second storage element.
2. The non-volatile storage system of claim 1 , wherein:
the one or more control circuits cause a forming voltage to be applied across the first storage element and the forming voltage to be applied across the second storage element during the first forming operation.
3. The non-volatile storage system of claim 1 , wherein:
the number of vertical bit lines in the second group of vertical bit lines is greater than the number of vertical bit lines in the first group of vertical bit lines.
4. The non-volatile storage system of claim 1 , wherein:
each word line comb of the plurality of word line combs is located at a different layer of a plurality of word line comb layers.
5. The non-volatile storage system of claim 1 , wherein:
the first word line comb is located above the second word line comb.
6. The non-volatile storage system of claim 1 , wherein:
the memory array is associated with a total number of word line comb layers, the plurality of word line combs comprises word line combs at a plurality of layers less than the total number of word line comb layers.
7. The non-volatile storage system of claim 1 , wherein:
the memory array is monolithically formed in one or more physical levels of memory cells having active areas disposed above a silicon substrate.
8. The non-volatile storage system of claim 1 , wherein:
the memory array comprises a three-dimensional memory array.
9. The non-volatile storage system of claim 1 , wherein:
each non-volatile storage element of the first set of non-volatile storage elements includes a reversible resistance-switching element without an isolation element in series with the reversible resistance-switching element.
10. A method for operating a non-volatile storage system, comprising:
determining a first group of vertical bit lines connected to a plurality of word line combs, the first group of vertical bit lines includes a first bit line, each word line comb of the plurality of word line combs is connected to the first bit line;
performing a first forming operation for a first set of non-volatile storage elements connected to the first group of vertical bit lines and the plurality of word line combs, the performing a first forming operation includes setting a first word line comb of the plurality of word line combs to a first voltage and setting a second word line comb of the plurality of word line combs to the first voltage, the first word line comb includes a first finger, the second word line comb includes a second finger, the performing a first forming operation includes setting a first vertical bit line of the first group of vertical bit lines to a second voltage less than the first voltage, the first vertical bit line is connected to the first finger via a first storage element and is connected to the second finger via a second storage element;
determining a second group of vertical bit lines connected to the plurality of word line combs different from the first group of vertical bit lines, the second group of vertical bit lines includes a second bit line, each word line comb of the plurality of word line combs is connected to the second bit line; and
performing a second forming operation for a second set of non-volatile storage elements connected to the second group of vertical bit lines and the plurality of word line combs, the second forming operation is performed subsequent to the first forming operation.
11. The method of claim 10 , wherein:
the setting a first vertical bit line to a second voltage includes setting the first vertical bit line to the second voltage such that a forming voltage is applied across the first storage element and the forming voltage is applied across the second storage element.
12. The method of claim 10 , wherein:
the number of vertical bit lines in the second group of vertical bit lines is greater than the number of vertical bit lines in the first group of vertical bit lines.
13. The method of claim 10 , wherein:
each word line comb of the plurality of word line combs is located at a different layer of a plurality of word line comb layers.
14. The method of claim 10 , wherein:
the first word line comb is located above the second word line comb.
15. The method of claim 10 , wherein:
the plurality of word line combs comprises word line combs at each layer of a plurality of word line comb layers.
16. The method of claim 10 , wherein:
the performing a first forming operation includes applying a forming voltage across non-volatile storage elements on all of the plurality of word line comb layers.
17. The method of claim 10 , wherein:
the first set of non-volatile storage elements is part of a memory array, the memory array is associated with a total number of word line comb layers, the plurality of word line combs comprises word line combs at a plurality of layers less than the total number of word line comb layers.
18. The method of claim 17 , wherein:
the memory array is monolithically formed in one or more physical levels of memory cells having active areas disposed above a silicon substrate.
19. The method of claim 10 , wherein:
the first set of non-volatile storage elements is part of a memory array, each non-volatile storage element of the first set of non-volatile storage elements includes a reversible resistance-switching element without an isolation element in series with the reversible resistance-switching element.
20. A non-volatile storage system, comprising:
a memory array, the memory array includes a first group of vertical bit lines connected to a plurality of word line combs, the first group of vertical bit lines includes a first bit line, each word line comb of the plurality of word line combs is connected to the first bit line, the memory array includes a second group of vertical bit lines connected to the plurality of word line combs, the second group of vertical bit lines includes a second bit line, each word line comb of the plurality of word line combs is connected to the second bit line, the number of vertical bit lines in the second group of vertical bit lines is greater than the number of vertical bit lines in the first group of vertical bit lines; and
one or more control circuits in communication with the memory array, the one or more control circuits cause a first voltage to be applied to a first word line comb of the plurality of word line combs and to a second word line comb of the plurality of word line combs, the first word line comb includes a first finger, the second word line comb includes a second finger, the one or more control circuits cause a second voltage less than the first voltage to be applied to a first vertical bit line of the first group of vertical bit lines, the first vertical bit line is connected to the first finger via a first storage element and is connected to the second finger via a second storage element, the one or more control circuits cause the second voltage to be applied to a second vertical bit line of the second group of vertical bit lines subsequent to applying the second voltage to the first vertical bit line, the second vertical bit line is connected to the first finger via a third storage element and is connected to the second finger via a fourth storage element.