Patent Assignment
Reel/Frame 038812/0954
CHANGE OF NAME
Recorded: 2016-05-25
Received: 2016-05-25
Pages: 18
Assignor
SANDISK TECHNOLOGIES INC
Executed: 2016-05-16
Assignee
SANDISK TECHNOLOGIES LLC
6900 DALLAS PARKWAY, SUITE 325, PLANO, TX, 75024, UNITED STATES
Covered Applications
(100)
NON-VOLATILE MEMORY DEVICE CONTAINING OXYGEN-SCAVENGING MATERIAL PORTIONS AND METHOD OF MAKING THEREOF
App. No. 15/157,945
→
Efficiently Managing Unmapped Blocks to Extend Life of Solid State Drive with Low Over-Provisioning
App. No. 15/157,367
→
Efficiently Managing Unmapped Blocks to Extend Life of Solid State Drive
App. No. 15/157,369
→
User Space Data Storage Management
App. No. 15/157,371
→
TIME DOMAIN RAMP RATE CONTROL FOR ERASE INHIBIT IN FLASH MEMORY
App. No. 15/155,957
→
SELF-ALIGNED ISOLATION DIELECTRIC STRUCTURES FOR A THREE-DIMENSIONAL MEMORY DEVICE
App. No. 15/155,639
→
STORAGE DEVICE BLISTER TRAY
App. No. 29/564,233
→
DUMMY WORD LINE CONTROL SCHEME FOR NON-VOLATILE MEMORY
App. No. 15/151,951
→
STORAGE DEVICE BLISTER TRAY
App. No. 29/564,230
→
STORAGE DEVICE BLISTER TRAY
App. No. 29/564,228
→
STORAGE DEVICE BLISTER TRAY
App. No. 29/564,232
→
USING NON-VOLATILE MEMORY BAD BLOCKS
App. No. 15/150,765
→
SENSE AMPLIFIER LOCAL FEEDBACK TO CONTROL BIT LINE VOLTAGE
App. No. 15/151,359
→
System, Method and Apparatus for Preventing Data Loss Due to Memory Defects Using Latches
App. No. 15/150,325
→
SYSTEMS AND METHODS FOR PROCESSING A SUBMISSION QUEUE
App. No. 15/148,409
→
MULTI-DIE DATA STORAGE DEVICE WITH IN-MEMORY PARITY CIRCUITRY
App. No. 15/145,897
→
Reduction of Write Amplification in Object Store
App. No. 15/144,704
→
Selective Removal Of Charge-Trapping Layer For Select Gate Transistor And Dummy Memory Cells In 3D Stacked Memory
App. No. 15/143,922
→
METHODS, SYSTEMS AND COMPUTER READABLE MEDIA FOR OPTIMIZING STORAGE DEVICE BUS AND RESOURCE UTILIZATION BY HOST REALIGNMENT
App. No. 15/143,538
→
SYSTEMS AND METHODS FOR PERFORMING DIRECT MEMORY ACCESS (DMA) OPERATIONS
App. No. 15/142,342
→
RESISTIVE MEMORY ELMENT EMPLOYING ELECTRON DENSITY MODULATION AND STRUCTURAL RELAXATION
App. No. 62/328,746
→
NON-VOLATILE MEMORY WITH IN FIELD FAILURE PREDICTION USING LEAKAGE DETECTION
App. No. 15/141,507
→
HIGH ACCURACY LEAKAGE DETECTION THROUGH LOW VOLTAGE BIASING
App. No. 62/328,412
→
NON-VOLATILE STORAGE ELEMENT WITH SUSPENDED CHARGE STORAGE REGION
App. No. 15/138,615
→
Storage System and Method for Using Hybrid Blocks with Sub-Block Erase Operations
App. No. 15/138,984
→
INDEPENDENT MULTI-PLANE READ AND LOW LATENCY HYBRID READ
App. No. 15/138,467
→
DYNAMIC RANDOM ACCESS MEMORY CELL INCLUDING ONE STEERING ELEMENT AND ONE RESISTIVE ELMENT AS AN EMBEDDED DEVICE
App. No. 62/327,292
→
ARRAY ARCHITECTURE
App. No. 62/326,720
→
Word Line-Dependent And Temperature-Dependent Pass Voltage During Programming
App. No. 15/136,429
→
Low Power VMCO ReRAM
App. No. 62/325,154
→
STORAGE SYSTEM AND METHOD FOR IMPROVED COMMAND FLOW
App. No. 15/134,104
→
DUMMY VOLTAGE TO REDUCE FIRST READ EFFECT IN MEMORY
App. No. 15/131,392
→
MULTI-DIE PROGRAMMING WITH DIE-JUMPING INDUCED PERIODIC DELAYS
App. No. 15/099,781
→
MEMORY INTERFACE COMMAND QUEUE THROTTLING
App. No. 15/099,653
→
Storage System and Method for Recovering Data Corrupted in a Host Memory Buffer
App. No. 15/099,018
→
Voltage Regulator With Fast Overshoot Settling Response
App. No. 15/099,491
→
Efficient Peak Current Management In A Multi-Die Stack
App. No. 15/099,496
→
Garbage Collection in Storage System with Distributed Processors
App. No. 15/098,282
→
THREE-DIMENSIONAL MEMORY DEVICE HAVING A TRANSITION METAL DICHALCOGENIDE CHANNEL
App. No. 15/094,552
→
MEMORY ERASE MANAGEMENT
App. No. 15/092,236
→
DATA STORAGE DEVICE HAVING INTERNAL TAGGING CAPABILITIES
App. No. 15/092,296
→
MULTILEVEL MEMORY STACK STRUCTURE EMPLOYING STACKS OF A SUPPORT PEDESAL STRUCTURE AND A SUPPORT PILLAR STRUCTURE
App. No. 62/316,883
→
FILAMENT CONFINEMENT IN REVERSIBLE RESISTANCE-SWITCHING MEMORY ELEMENTS
App. No. 15/088,902
→
OUT OF ORDER READ TRANSFER WITH HOST MEMORY BUFFER
App. No. 15/088,692
→
Systems and Methods for Decoupling Host Commands in a Non-Volatile Memory System
App. No. 15/088,596
→
CONFORMAL DEPOSITION SYSTEM EMPLOYING MULTIPLE TEMPERATURE ZONES
App. No. 62/316,647
→
ESD CENTRIC LOW-COST IO LAYOUT DESIGN TOPOLOGY
App. No. 15/087,004
→
SELF-DETECTING A HEATING EVENT TO NON-VOLATILE STORAGE
App. No. 15/087,242
→
CONTROLLING MEMORY CELL SIZE IN THREE DIMENSIONAL NONVOLATILE MEMORY
App. No. 15/087,980
→
NAND Structure With Tier Select Gate Transistors
App. No. 62/316,557
→
METHOD AND SYSTEM FOR MANAGING DATA IN NON-VOLATILE MEMORY
App. No. 15/087,104
→
ROBUST NUCLEATION LAYERS FOR ENHANCED FLUORINE PROTECTION AND STRESS REDUCTION IN 3D NAND WORD LINES
App. No. 15/086,702
→
APPARATUS AND METHODS FOR SENSING HARD BIT AND SOFT BITS
App. No. 15/087,379
→
IMPLEMENTATION OF VMCO AREA SWITCHING CELL TO VBL ARCHITECTURE
App. No. 15/085,813
→
METHOD AND SYSTEM FOR BLENDING DATA RECLAMATION AND DATA INTEGRITY GARBAGE COLLECTION
App. No. 62/315,526
→
METHOD AND SYSTEM FOR COMPACTING DATA IN NON-VOLATILE MEMORY
App. No. 15/083,723
→
System and Method for Erase Detection before Programming of a Storage Device
App. No. 15/084,100
→
OPERATION MODES FOR AN INVERTED NAND ARCHITECTURE
App. No. 15/083,224
→
TEMPERATURE INDEPENDENT REFERENCE CURRENT GENERATION FOR CALIBRATION
App. No. 15/082,241
→
SYSTEMS AND METHODS FOR STORAGE COLLISION MANAGEMENT
App. No. 15/080,161
→
VERTICAL NAND AND METHOD OF MAKING THEREOF USING SEQUENTIAL STACK ETCHING AND SELF-ALIGNED LANDING PAD
App. No. 15/080,269
→
THREE DIMENSIONAL NAND MEMORY DEVICE WITH COMMON BIT LINE FOR MULTIPLE NAND STRINGS IN EACH MEMORY BLOCK
App. No. 15/078,555
→
ERROR CORRECTION CODE PROCESSING AND DATA SHAPING FOR REDUCING WEAR TO A MEMORY
App. No. 15/073,373
→
DATA CODING
App. No. 15/073,215
→
WEARABLE DEVICE WITH RECEPTACLE TO RECEIVE AN AUDIO DEVICE AND METHOD OF OPERATING SAME
App. No. 15/073,390
→
THREE-DIMENSIONAL MEMORY DEVICE CONTAINING ANNULAR ETCH-STOP SPACER AND METHOD OF MAKING THEREOF
App. No. 15/071,575
→
DATA REGISTER COPYING FOR NON-VOLATILE STORAGE ARRAY OPERATIONS
App. No. 15/071,100
→
APPARATUS AND METHOD FOR PRECONDITIONING CURRENTS TO REDUCE ERRORS IN SENSING FOR NON-VOLATILE MEMORY
App. No. 15/069,287
→
CHARGE PUMP BASED OVER-SAMPLING WITH UNIFORM STEP SIZE FOR CURRENT DETECTION
App. No. 15/068,053
→
TECHNIQUES FOR PROGRAMMING OF SELECT GATES IN NAND MEMORY
App. No. 15/062,987
→
Adaptive Determination Of Program Parameter Using Program Of Erase Rate
App. No. 15/062,661
→
MULTI-STAGE DECODER
App. No. 15/061,246
→
OPEN BLOCK SOURCE BIAS ADJUSTMENT FOR AN INCOMPLETELY PROGRAMED BLOCK OF A NONVOLATILE STORAGE DEVICE
App. No. 15/061,919
→
MULTI-TYPE PARITY BIT GENERATION FOR ENCODING AND DECODING
App. No. 62/303,899
→
CONVOLUTIONAL LOW-DENSITY PARITY-CHECK CODING
App. No. 62/303,768
→
TEMPERATURE VARIATION COMPENSATION
App. No. 62/303,891
→
ERASURE CORRECTING CODING USING DATA SUBSETS AND PARTIAL PARITY SYMBOLS
App. No. 62/304,113
→
MEMORY DIE TEMPERATURE ADJUSTMENT BASED ON AGING CONDITION
App. No. 15/061,702
→
ECC DECODING USING RAID-TYPE PARITY
App. No. 62/303,975
→
DYNAMIC-SHIFTING REDUNDANCY MAPPING FOR NON-VOLATILE DATA STORAGE
App. No. 15/061,856
→
SKELETON I/O GENERATION FOR EARLY ESD ANALYSIS
App. No. 62/303,748
→
ECC AND RAID-TYPE DECODING
App. No. 62/303,844
→
PROGRAM SEQUENCING
App. No. 15/061,940
→
Erase Health Metric to Rank Memory Portions
App. No. 62/303,244
→
Mobile Device and Method for Synchronizing Use of the Mobile Device's Communications Port Among a Plurality of Applications
App. No. 15/059,000
→
THREE-DIMENSIONAL MEMORY DEVICE WITH CHARGE-TRAPPING-FREE GATE DIELECTRIC FOR TOP SELECT GATE ELECTRODE AND METHOD OF MAKING THEREOF
App. No. 15/056,510
→
METHOD OF MAKING SELF-ASSEMBLING FLOATING GATE ELECTRODES FOR A THREE-DIMENSIONAL MEMORY DEVICE
App. No. 15/056,465
→
NON-VOLATILE MEMORY WITH CORRUPTION RECOVERY
App. No. 15/056,070
→
RECESSED INTEGRATED VERTICAL BIT LINE FOR A RESISTIVE RANDOM ACCESS MEMORY
App. No. 62/300,262
→
ENHANCEMENT OF THERMAL STABILITY OF COBALT-CONTAINING CONDUCTIVE LAYERS IN A MEMORY STRUCTURE
App. No. 62/300,221
→
DATA STORAGE DEVICE WITH TEMPERATURE SENSOR AND TEMPERATURE CALIBRATION CIRCUITRY AND METHOD OF OPERATING SAME
App. No. 15/054,613
→
Memory System and Method for Fast Firmware Download
App. No. 15/055,166
→
SINGLE CHAMBER MULTI-POSITION DEPOSITION TOOL FOR A STACK OF REPEATED MATERIAL COMPOSITIONS
App. No. 62/299,621
→
Coalescing Metadata and Data Writes via Write Serialization with Device-Level Address Remapping
App. No. 62/298,929
→
METHODS, SYSTEMS, AND COMPUTER READABLE MEDIA FOR STORAGE DEVICE WORKLOAD DETECTION USING POWER CONSUMPTION
App. No. 15/051,254
→
Efficient Implementation of Optimized Host-Based Garbage Collection Strategies Using Xcopy and Arrays of Flash Devices
App. No. 62/298,936
→
Efficient Implementation of Optimized Host-Based Garbage Collection Strategies Using Xcopy and Multiple Logical Stripes
App. No. 62/298,939
→
Memory-Efficient Block/Object Address Mapping
App. No. 62/298,925
→
THREE DIMENSIONAL MEMORY DEVICE CONTAINING DISCRETE SILICON NITRIDE CHARGE STORAGE REGIONS
App. No. 15/049,444
→
ADAPTIVE HOST MEMORY BUFFER (HMB) CACHING USING UNASSISTED HINTING
App. No. 15/050,364
→