Storage system and method for using hybrid blocks with sub-block erase operations

1. A storage system comprising:

a memory comprising a block, wherein the block comprises a first sub-block and a second sub-block; and

a controller in communication with the memory, wherein the controller is configured to:

erase the first sub-block, wherein the second sub-block is programmed;

program the first sub-block to fewer bits per cell than the second sub-block is programmed to; and

move data programmed in the first sub-block to a block having more bits per cell than the first sub-block.

2. The storage system of claim 1 , wherein the memory comprises a three-dimensional memory.

3. The storage system of claim 1 , wherein the first sub-block is programmed using a single level cell (SLC) mode, and wherein the second sub-block is programmed using a multi-level cell (MLC) mode.

4. The storage system of claim 1 , wherein the block comprises at least one additional sub-block.

5. The storage system of claim 1 , wherein the first and second sub-blocks are the same size.

6. The storage system of claim 1 , wherein the first and second sub-blocks are different sizes.

7. The storage system of claim 1 , wherein the block comprises a plurality of word lines, and wherein a programming order of the word lines starts with the word lines in the first sub-block.

8. The storage system of claim 1 , wherein the storage system is embedded in a host.

9. The storage system of claim 1 , wherein the storage system is removably connected to a host.

10. A method comprising:

performing the following in a storage system comprising a memory comprising a block:

erasing a first portion of the block while leaving a second portion of the block with data written in it;

writing data in the first portion of the block using a write mode that is characterized by a lower bit error rate than a write mode used to write data in the second portion of the block; and

moving data programmed in the first portion to a block having more bits per cell than the first portion.

11. The method of claim 10 , wherein the memory comprises a three-dimensional memory.

12. The method of claim 10 , wherein the first portion is programmed using a single level cell (SLC) mode, and wherein the second portion is programmed using a multi-level cell (MLC) mode.

13. The method of claim 10 , wherein the block comprises at least one additional portion.

14. The method of claim 10 , wherein the first and second portions are the same size.

15. The method of claim 10 , wherein the first and second portions are different sizes.

16. The method of claim 10 , wherein the block comprises a plurality of word lines, and wherein a programming order of the word lines starts with the word lines in the first portion.

17. The method of claim 10 , wherein the storage system is embedded in a host.

18. The method of claim 10 , wherein the storage system is removably connected to a host.

19. A storage system comprising:

a memory comprising a block, wherein the block comprises a first sub-block and a second sub-block;

means for erasing the first sub-block, wherein the second sub-block is programmed;

means for programming the first sub-block to fewer bits per cell than the second sub-block is programmed to; and

means for moving data programmed in the first sub-block to a block having more bits per cell than the first sub-block.

20. The storage system of claim 19 , wherein the memory comprises a three-dimensional memory.

21. The storage system of claim 19 , wherein the storage system is embedded in a host.

22. The storage system of claim 19 , wherein the storage system is removably connected to a host.