Multi-die programming with die-jumping induced periodic delays
View Patent ↗Systems and methods for improving the reliability of data stored in memory cells are described. To mitigate the effects of trapped electrons after one or more programming pulses have been applied to memory cells, a delay between the one or more programming pulses and subsequent program verify pulses may be set based on a chip temperature, the number of the one or more programming pulses that were applied to the memory cells, and/or the programming voltage that was applied to the memory cells during the one or more programming pulses. To mitigate the effects of residual electrons after one or more program verify pulses have been applied to memory cells, a delay between the one or more program verify pulses and subsequent programming pulses may be set based on a chip temperature and/or the programming voltage to be applied to the memory cells during the subsequent programming pulses.
1. A system, comprising:
a memory array including a set of memory cells;
a program circuit configured to apply one or more programming pulses to the set of memory cells and subsequent to one of the programming pulses apply one or more program verify pulses to the set of memory cells after a time delay, the one or more programming pulses includes a programming pulse at a programming voltage; and
a delay circuit configured to determine the time delay between the one or more programming pulses and the one or more program verify pulses based on the programming voltage, the delay circuit configured to determine a second programming voltage different from the programming voltage to be applied to the set of memory cells and determine a second time delay between the one or more program verify pulses and the application of a second set of programming pulses to the set of memory cells based on the second programming voltage.
2. The system of claim 1 , wherein:
the delay circuit configured to determine a chip temperature and determine the time delay based on the chip temperature.
3. The system of claim 1 , wherein:
the delay circuit configured to determine a number of programming pulses that were applied to the set of memory cells and determine the time delay based on the number of programming pulses that were applied to the set of memory cells.
4. The system of claim 1 , wherein:
the delay circuit configured to determine a programming loop count for the set of memory cells and determine the time delay based on the programming loop count.
5. The system of claim 1 , wherein:
the delay circuit configured to determine the second time delay based on a chip temperature.
6. The system of claim 1 , wherein:
the delay circuit configured to set the time delay to a first time delay if the chip temperature is below a temperature threshold and set the second time delay to a second time delay different from the first time delay if the chip temperature is below the temperature threshold.
7. The system of claim 1 , wherein:
the program circuit configured to apply the second set of programming pulses to a second set of memory cells prior to the one or more program verify pulses being applied to the set of memory cells.
8. The system of claim 7 , wherein:
the set of memory cells is arranged on a first memory die; and
the second set of memory cells is arranged on a second memory die.
9. The system of claim 1 , wherein:
the memory array comprises a non-volatile memory that is monolithically formed in one or more physical levels of memory cells having active areas disposed above a silicon substrate.
10. A method, comprising:
applying one or more programming pulses to a set of memory cells, the one or more programming pulses include a programming pulse at a programming voltage;
determining a time delay between the one or more programming pulses and one or more program verify pulses based on the programming voltage;
applying the one or more program verify pulses to the set of memory cells after the time delay;
determining a second programming voltage different from the programming voltage to be applied to the set of memory cells; and
determining a second time delay between the one or more program verify pulses being applied to the set of memory cells and a second set of programming pulses being applied to the set of memory cells based on the second programming voltage.
11. The method of claim 10 , further comprising:
determining a chip temperature, the determining the time delay includes determining the time delay based on the chip temperature.
12. The method of claim 10 , further comprising:
determining a number of programming pulses that were applied to the set of memory cells, the determining the time delay includes determining the time delay based on the number of programming pulses that were applied to the set of memory cells.
13. The method of claim 10 , further comprising:
determining a programming loop count for the set of memory cells, the determining the time delay includes determining the time delay based on the programming loop count.
14. The method of claim 10 , further comprising:
applying the second set of programming pulses to a second set of memory cells prior to the one or more program verify pulses being applied to the set of memory cells.
15. The method of claim 14 , wherein:
the set of memory cells is arranged on a first memory die; and
the second set of memory cells is arranged on a second memory die.
16. An apparatus, comprising:
a memory array including a set of memory cells;
a program circuit configured to apply a first programming pulse to the set of memory cells and apply a first program verify pulse to the set of memory cells after a first time delay from application of the first programming pulse to the set of memory cells, the program circuit configured to apply a second programming pulse to the set of memory cells and apply a second program verify pulse to the set of memory cells after a second time delay from application of the second programming pulse, the second programming pulse is greater than the first programming pulse, the second time delay is greater than the first time delay; and
a delay circuit configured to determine a chip temperature, the delay circuit configured to determine the first time delay based on a magnitude of the first programming pulse and the chip temperature, the delay circuit configured to determine the second time delay based on a magnitude of the second programming pulse and the chip temperature, the delay circuit configured to determine a second programming voltage corresponding with the second programming pulse and determine a third time delay between the first program verify pulse and the application of the second programming pulse based on the second programming voltage.