Program sequencing

1. An apparatus comprising:

a block of non-volatile storage cells comprising a plurality of word lines, the word lines organized into a monotonically increasing sequence; and

a controller for the block, the controller configured to:

determine a set of storage cells of a word line that are to be programmed to one or more storage states above a predetermined threshold;

determine a set of storage cells of a previous word line adjacent to and before the word line in the sequence that are to be programmed to one or more storage states below the predetermined threshold;

program the set of storage cells of the word line to the one or more storage states above the predetermined threshold; and

program the set of storage cells of the previous word line to the one or more storage states below the predetermined threshold after programming the set or storage cells of the word line to the one or more storage states above the predetermined threshold, wherein the word line and the previous word line share at least a charge trap layer such that a fringing field from programming the word line injects charge into the previous word line.

2. The apparatus of claim 1 , wherein the controller is configured to iterate through the word lines of the block, programming sets of storage cells of successive word lines to the one or more storage states above the predetermined threshold before programming sets of storage cells of previous word lines to the one or more storage states below the predetermined threshold.

3. The apparatus of claim 2 , wherein the controller is configured to iterate through the word lines of the block until each word line comprises a set of storage cells programmed to the one or more storage states above the predetermined threshold and a set of storage cells programmed to the one or more storage states below the predetermined threshold.

4. The apparatus of claim 3 , wherein the controller is configured to, for each of the word lines of the block, program the set of storage cells programmed to the one or more storage states above the predetermined threshold before programming the set of storage cells programmed to the one or more storage states below the predetermined threshold.

5. The apparatus of claim 1 , wherein the word line is physically adjacent to the previous word line and has a higher word line address in the monotonically increasing sequence than a word line address of the previous word line.

6. The apparatus of claim 1 , wherein the controller is configured to organize the word lines into the monotonically increasing sequence using addresses of the word lines.

7. The apparatus of claim 1 , wherein the controller comprises a hardware storage controller in communication with a plurality of semiconductor chips of non-volatile storage, one of the semiconductor chips comprising the block of non-volatile storage cells.

8. The apparatus of claim 1 , wherein the controller comprises a state machine on the same semiconductor chip as the block of non-volatile storage cells.

9. The apparatus of claim 1 , wherein the controller comprises a device driver for a non-volatile storage device comprising the block of non-volatile storage cells, the device driver comprising a non-transitory computer readable storage medium storing executable code of the controller.

10. A method comprising:

determining a group of memory cells of a first word line that are to be programmed to one or more charge levels greater than a threshold level;

determining a group of memory cells of a word line having a lower word line address than the first word line that are to be programmed to one or more charge levels greater than the threshold level;

determining a group of memory cells of a word line having a higher word line address than the first word line that are to be programmed to one or more charge levels lower than the threshold level;

programming the group of memory cells of the first word line to the one or more charge levels greater than the threshold level;

programming the group of memory cells of a word line having a lower word line address than the first word line to the one or more charge levels lower than the threshold level after programming the group of memory cells of the first word line to the one or more charge levels greater than the threshold level; and

programming the group of memory cells of a word line having a higher word line address than the first word line to the one or more charge levels greater than the threshold level after programming the group of memory cells of the word line having a lower word line address to the one or more charge levels lower than the threshold level.

11. The method of claim 10 , further comprising programming a different group of memory cells of the first word line to the one or more charge levels lower than the threshold level after programming the group of memory cells of the word line having the higher word line address to the one or more charge levels greater than the threshold level.

12. The method of claim 10 , further comprising iterating through additional word lines of a same erase block as the first word line, programming groups of memory cells of successive word lines in a word line address order to the one or more charge levels greater than the threshold level before programming groups of memory cells of previous word lines to the one or more charge levels lower than the threshold level.

13. The method of claim 10 , wherein the first word line, the word line having a lower word line address, and the word line having a higher word line address are part of the same set of strings of three dimensional NAND structures.

14. The method of claim 13 , further comprising interleaving the programming of word lines of one or more additional sets of strings of three dimensional NAND structures in the same order as the programming of the first word line, the word line having a lower word line address, and the word line having a higher word line address.

15. The method of claim 1 , wherein the first word line is physically adjacent to and between the word line having the lower word line address and the word line having the higher word line address.

16. An apparatus comprising:

means for determining which cells of a non-volatile memory medium are to be programmed to one or more states above a read voltage threshold and which cells are to be programmed to one or more states below the read voltage threshold, the non-volatile memory medium comprising a monotonically increasing series of word lines of cells; and

means for programming cells of subsequent word lines in the monotonically increasing series to the one or more states above the read voltage threshold prior to programming cells of previous word lines in the monotonically increasing series to the one or more states below the read voltage threshold such that one or more cells of a previous word line are not programmed to the one or more states below the read voltage threshold until after one or more cells of a subsequent word line have been programmed to the one or more states above the read voltage threshold, wherein the read voltage threshold is between about 2 and about 4 volts.

17. The apparatus of claim 16 , further comprising means for interleaving the programming of word lines of one or more additional sets of strings of three dimensional NAND structures between the programming of the monotonically increasing series of word lines of cells in a same order as the programming of the monotonically increasing series of word lines of cells, the monotonically increasing series of word lines of cells being part of the same set of strings of three dimensional NAND structures.

18. The apparatus of claim 16 , wherein the read voltage threshold is between about 2.5 and about 3.5 volts.