Memory cells having storage elements that share material layers with steering elements and methods of forming the same
View Patent ↗A memory cell is provided that includes a steering element, a metal-insulator-metal stack coupled in series with the steering element, and a conductor above the metal-insulator-metal stack. The steering element includes a diode having an n-region and a p-region. The metal-insulator-metal stack includes a reversible resistivity-switching material between a top electrode and a bottom electrode, and the top electrode includes a highly doped semiconductor material. The memory cell does not include a metal layer disposed between the metal-insulator-metal stack and the conductor. The bottom electrode includes the n-region or the p-region of the diode, and the reversible resistivity-switching material is directly adjacent the n-region or the p-region of the diode. Numerous other aspects are provided.
1. A memory cell comprising:
a steering element comprising a diode having an n-region and a p-region;
a metal-insulator-metal (“MIM”) stack coupled in series with the steering element, wherein the MIM stack comprises a reversible resistivity-switching (“RRS”) material disposed between a top electrode and a bottom electrode, and the top electrode comprises a highly doped semiconductor material; and
a conductor disposed above the MIM stack,
wherein the memory cell does not include a metal layer disposed between the MIM stack and the conductor, and
wherein the bottom electrode comprises the n-region or the p-region of the diode and the RRS material is disposed directly adjacent the n-region or the p-region of the diode.
2. The memory cell of claim 1 , wherein the steering element comprises a vertically oriented diode.
3. The memory cell of claim 1 , wherein the steering element comprises a p-n or p-i-n diode.
4. The memory cell of claim 1 , wherein the MIM stack is disposed above or below the steering element.
5. The memory cell of claim 1 , wherein the RRS material comprises one or more of HfO x , ZrO x , NiO x , TiO x , Ta x O y , NbO x and Al X O Y .
6. The memory cell of claim 1 , wherein the top electrode comprises one of p+ silicon, p+ silicon-germanium, n+ silicon, and n+ silicon-germanium.
7. The memory cell of claim 1 , wherein the MIM stack comprises a portion of the steering element.
8. The memory cell of claim 1 , wherein the bottom electrode comprises a highly doped semiconductor material.
9. The memory cell of claim 8 , wherein the bottom electrode comprises one of p+ silicon, p+ silicon-germanium, n+ silicon, and n+ silicon-germanium.
10. A monolithic three-dimensional memory array comprising:
a first memory level monolithically formed above a substrate, the first memory level comprising a plurality of memory cells, wherein each memory cell comprises:
a steering element comprising a diode having an n-region and a p-region;
a metal-insulator-metal (“MIM”) stack coupled in series with the steering element, wherein the MIM stack comprises a reversible resistance-switching (“RRS”) material disposed between a top electrode and a bottom electrode, and the top electrode comprises a highly doped semiconductor material; and
a conductor disposed above the MIM stack,
wherein the memory cell does not include a metal layer disposed between the MIM stack and the conductor, and
wherein the bottom electrode comprises the n-region or the p-region of the diode and the RRS material is disposed directly adjacent the n-region or the p-region of the diode; and
a second memory level monolithically formed above the first memory level.
11. The monolithic three-dimensional memory array of claim 10 , wherein the steering element comprises a vertically oriented diode.
12. The monolithic three-dimensional memory array of claim 10 , wherein the steering element comprises a p-n or p-i-n diode.
13. The monolithic three-dimensional memory array of claim 10 , wherein each MIM stack is disposed above or below the steering element.
14. The monolithic three-dimensional memory array of claim 10 , wherein the RRS material comprises one or more of HfO x , ZrO x , NiO x , TiO x , Ta x O y , NbO x and Al X O Y .
15. The monolithic three-dimensional memory array of claim 10 , wherein the top electrode comprises one of p+ silicon, p+ silicon-germanium, n+ silicon, and n+ silicon-germanium.
16. The monolithic three-dimensional memory array of claim 10 , wherein the MIM stack comprises a portion of the steering element.
17. The monolithic three-dimensional memory array of claim 10 , wherein the bottom electrode comprises a highly doped semiconductor material.
18. The monolithic three-dimensional memory array of claim 17 , wherein the bottom electrode comprises one of p+ silicon, p+ silicon-germanium, n+ silicon, and n+ silicon-germanium.
19. A non-volatile memory that is monolithically formed in one or more physical levels of arrays of memory cells having an active area disposed above a silicon substrate, wherein each of the memory cells comprises:
a steering element comprising a diode having an n-region and a p-region;
a metal-insulator-metal (“MIM”) stack coupled in series with the steering element, wherein the MIM stack comprises a reversible resistivity-switching (“RRS”) material disposed between a top electrode and a bottom electrode, and the top electrode comprises a highly doped semiconductor material; and
a conductor disposed above the MIM stack,
wherein the memory cell does not include a metal layer disposed between the MIM stack and the conductor, and
wherein the bottom electrode comprises the n-region or the p-region of the diode and the RRS material is disposed directly adjacent the n-region or the p-region of the diode.
20. The non-volatile memory of claim 19 , wherein the RRS material comprises one or more of HfO x , ZrO x , NiO x , TiO x , Ta x O y , NbO x and Al X O Y .