Compensation scheme for non-volatile memory
Methods for performing parallel voltage and current compensation during reading and/or writing of memory cells in a memory array are described. In some embodiments, the compensation may include adjusting a bit line voltage and/or bit line reference current applied to a memory cell based on a memory array zone, a bit line layer, and a memory cell direction associated with the memory cell. The compensation may include adjusting the bit line voltage and/or bit line reference current on a per memory cell basis depending on memory cell specific characteristics. In some embodiments, a read/write circuit for reading and/or writing a memory cell may select a bit line voltage from a plurality of bit line voltage options to be applied to the memory cell based on whether the memory cell has been characterized as a strong, weak, or typical memory cell.
1. A monolithic three-dimensional integrated circuit, comprising:
a three-dimensional memory array including a first layer of memory cells and a second layer of memory cells, the first layer of memory cells includes a first memory cell, the second layer of memory cells includes a second memory cell, the first memory cell is located above the second memory cell, the second memory cell is located above a substrate, the first memory cell and the second memory cell are formed above the substrate without any intervening substrates between the first memory cell and the second memory cell; and
supporting circuitry in communication with the three-dimensional memory array, the supporting circuitry generates a plurality of bit line voltage options associated with a programming operation, the supporting circuitry determines a state associated with the first memory cell and determines an upper current threshold based on the state, the supporting circuitry selects a first bit line voltage of the plurality of bit line voltage options based on whether an output current associated with the first memory cell is greater than the upper current threshold, the supporting circuitry causes the programming operation to be performed to the first memory cell, the first bit line voltage is applied to the first memory cell during the programming operation.
2. The monolithic three-dimensional integrated circuit of claim 1 , wherein:
the first memory cell and the second memory cell are arranged in a vertical column that is perpendicular to the substrate.
3. The monolithic three-dimensional integrated circuit of claim 1 , wherein:
the first memory cell and the second memory cell are located within a vertical plane that is perpendicular to the substrate.
4. The monolithic three-dimensional integrated circuit of claim 1 , wherein:
the first memory cell and the second memory cell are in communication with a first bit line, the first bit line is arranged in a vertical direction that is perpendicular to the substrate, the first bit line voltage is applied to the first bit line during the programming operation.
5. The monolithic three-dimensional integrated circuit of claim 1 , wherein:
the first layer of memory cells includes a third memory cell, the second layer of memory cells includes a fourth memory cell, the third memory cell is located above the fourth memory cell, the first memory cell and the third memory cell are arranged in a first horizontal plane, the second memory cell and the fourth memory cell are arranged in a second horizontal plane that is below the first horizontal plane.
6. The monolithic three-dimensional integrated circuit of claim 1 , wherein:
the three-dimensional memory array and the supporting circuitry are integrated within the monolithic three-dimensional integrated circuit.
7. The monolithic three-dimensional integrated circuit of claim 6 , wherein:
the three-dimensional memory array is fabricated above the supporting circuitry.
8. The monolithic three-dimensional integrated circuit of claim 1 , wherein:
the supporting circuitry determines whether the first memory cell is located at a near end of a word line connected to the first memory cell, the supporting circuitry selects the first bit line voltage of the plurality of bit line voltage options based on whether the first memory cell is located at the near end of the word line.
9. The monolithic three-dimensional integrated circuit of claim 1 , wherein:
the supporting circuitry selects the first bit line voltage of the plurality of bit line voltage options based on whether the first memory cell comprises a near-near memory cell.
10. The monolithic three-dimensional integrated circuit of claim 1 , wherein:
the supporting circuitry generates the plurality of bit line voltage options based on at least one of a memory array zone associated with the first memory cell or a memory cell direction associated with the first memory cell.
11. A method for operating a monolithic three-dimensional integrated circuit, comprising:
generating a plurality of bit line voltage options associated with a programming operation for a three-dimensional memory array, the three-dimensional memory array includes a first memory cell and a second memory cell arranged in a vertical column that is perpendicular to a substrate, the first memory cell is located above the second memory cell, the second memory cell is located above the substrate;
determining a state associated with the first memory cell;
determining an upper current threshold based on the state;
selecting a first bit line voltage of the plurality of bit line voltage options based on whether an output current associated with the first memory cell is greater than the upper current threshold; and
applying the first bit line voltage to the first memory cell during the programming operation.
12. The method of claim 11 , wherein:
the first memory cell and the second memory cell are in communication with a first bit line, the first bit line is arranged in a vertical direction that is perpendicular to the substrate, the first bit line voltage is applied to the first bit line during the programming operation.
13. The method of claim 11 , wherein:
the three-dimensional memory array includes a third memory cell and a fourth memory cell, the third memory cell is located above the fourth memory cell, the first memory cell and the third memory cell are arranged in a first horizontal plane, the second memory cell and the fourth memory cell are arranged in a second horizontal plane that is below the first horizontal plane.
14. The method of claim 11 , wherein:
the selecting a first bit line voltage includes selecting the first bit line voltage based on whether the first memory cell is located at a near end of a word line connected to the first memory cell.
15. The method of claim 11 , wherein:
the generating a plurality of bit line voltage options includes generating the plurality of bit line voltage options based on at least one of a memory array zone associated with the first memory cell or a memory cell direction associated with the first memory cell.