Methods and apparatus for layout of three dimensional matrix array memory for reduced cost patterning
View Patent ↗Apparatus, methods, and systems are provided for a memory layer layout for a three-dimensional memory. The memory layer includes a plurality of memory array blocks; a plurality of memory lines coupled thereto; and a plurality of zia contact areas for coupling the memory layer to other memory layers in a three-dimensional memory. The memory lines extend from the memory array blocks, are formed using a sidewall defined process, and have a half pitch dimension smaller than the nominal minimum feature size capability of a lithography tool used in forming the memory lines. The zia contact areas have a dimension that is approximately four times the half pitch dimension of the memory lines. The memory lines are arranged in a pattern that allows a single memory line to intersect a single zia contact area and to provide area between other memory lines for other zia contact areas. Other aspects are disclosed.
1. A three-dimensional memory array comprising:
a memory array layer including an array and a plurality of memory lines wherein portions of the memory lines extend from the array substantially parallel to each other,
wherein a first subset of the memory lines extend from a first side of the array,
wherein a second subset of the memory lines extend from a second side of the array,
wherein within the first subset of memory lines a first plurality of memory lines terminate proximate an edge of the array,
wherein within the first subset of memory lines a second plurality of memory lines extend beyond the edge of the array into a contact region,
wherein the contact region includes a plurality of contacts adapted to couple the second plurality of memory lines to support circuitry,
wherein the contacts are disposed in two or more rows, the contact rows disposed substantially non-parallel to the memory lines, and
wherein adjacent memory lines couple to contacts in different rows.
2. The three-dimensional memory array of claim 1 wherein the contacts are zias.
3. The three-dimensional memory array of claim 1 wherein the first subset of memory lines is substantially equal in number to the second subset of memory lines.
4. The three-dimensional memory array of claim 1 wherein the first plurality of memory lines is substantially equal in number to the second plurality of memory lines.
5. The three-dimensional memory array of claim 1 wherein the first plurality of memory lines are grouped in pairs.
6. The three-dimensional memory array of claim 1 wherein the first plurality of memory lines are grouped in groups of four lines.
7. The three-dimensional memory array of claim 1 wherein the first plurality of memory lines are grouped in groups of more than two lines.
8. The three-dimensional memory array of claim 1 wherein the memory lines are formed by pitch doubling processing techniques.
9. The three-dimensional memory array of claim 1 wherein the first plurality of memory lines are terminated by a cut mask process.
10. The three-dimensional memory array of claim 1 wherein the cut mask process uses a cut mask pattern that includes at least two cut mask shapes,
wherein each cut mask shape is disposed at a different edge of the array and associated with a group of memory lines.
11. The three-dimensional memory array of claim 1 wherein the second plurality of memory lines extend beyond the contact region to a second array.
12. The three-dimensional memory array of claim 1 wherein the first and second pluralities of memory lines each include an even number of memory lines.
13. The three-dimensional memory array of claim 1 wherein the first and second pluralities of memory lines together include an even number of memory lines.