Memory hole bit line structures
View Patent ↗Methods for reducing leakage currents through unselected memory cells of a memory array during a memory operation are described. In some cases, the leakage currents through the unselected memory cells of the memory array may be reduced by setting an adjustable resistance bit line structure connected to the unselected memory cells into a non-conducting state. The adjustable resistance bit line structure may comprise a bit line structure in which the resistance of an intrinsic (or near intrinsic) polysilicon portion of the bit line structure may be adjusted via an application of a voltage to a select gate portion of the bit line structure that is not directly connected to the intrinsic polysilicon portion. The intrinsic polysilicon portion may be set into a conducting state or a non-conducting state based on the voltage applied to the select gate portion.
1. A non-volatile memory, comprising: a memory element layer; an adjustable resistance local bit line entirely surrounded by the memory element layer in a first dimension; a dielectric layer entirely surrounded by the adjustable resistance local bit line in the first dimension; a select gate entirely surrounded by the dielectric layer in the first dimension, the select gate is electrically isolated from the adjustable resistance local bit line by the dielectric layer in the first dimension; and a word line, a portion of the memory element layer arranged between the word line and the adjustable resistance local bit line, the word line is arranged above a substrate, the first direction is orthogonal to a surface of the substrate.
2. The non-volatile memory of claim 1 , wherein:
the non-volatile memory configured to set a resistance of the adjustable resistance local bit line based on a first voltage applied to the select gate.
3. The non-volatile memory of claim 2 , wherein:
the non-volatile memory configured to set the adjustable resistance local bit line into a non-conducting state based on the first voltage applied to the select gate.
4. The non-volatile memory of claim 1 , wherein:
the adjustable resistance local bit line comprises one of undoped polysilicon, undoped silicon germanium, or undoped indium gallium arsenide.
5. The non-volatile memory of claim 1 , wherein:
the memory element layer comprises a ReRAM material; and
the dielectric layer comprises one of silicon dioxide or silicon nitride.
6. The non-volatile memory of claim 1 , wherein:
the adjustable resistance local bit line comprises a vertical bit line that is substantially orthogonal to the substrate.
7. The non-volatile memory of claim 1 , wherein:
the adjustable resistance local bit line is connected to a global bit line via an integrated resistor arranged between the adjustable resistance local bit line and the global bit line.
8. The non-volatile memory of claim 1 , wherein:
the adjustable resistance local bit line is connected to a global bit line, the global bit line is in communication with a sense amplifier during a memory operation.
9. The non-volatile memory of claim 1 , wherein:
the select gate comprises a substantially cylindrical pillar.
10. The non-volatile memory of claim 1 , wherein:
a thin-film transistor connects a select gate line to the select gate, the adjustable resistance local bit line is set into a non-conducting state based on a first voltage applied to the select gate via the thin-film transistor.
11. A non-volatile memory, comprising:
a memory element layer;
a layer of undoped polysilicon at least partially enclosed by the memory element layer in a first dimension;
a dielectric layer at least partially enclosed by the layer of undoped polysilicon in the first dimension;
a select gate at least partially enclosed by the dielectric layer in the first dimension, the select gate is electrically isolated from the layer of undoped polysilicon by the dielectric layer in the first dimension; and
a word line, a portion of the memory element layer arranged between the word line and the layer of undoped polysilicon, the layer of undoped polysilicon is connected to a global bit line, the word line is arranged above a substrate, the first direction is perpendicular to a surface of the substrate.
12. The non-volatile memory of claim 11 , wherein:
the non-volatile memory configured to set the layer of undoped polysilicon into a non-conducting state based on a first voltage applied to the select gate.
13. The non-volatile memory of claim 11 , wherein:
the memory element layer includes a ReRAM material; and
the dielectric layer comprises silicon dioxide.
14. The non-volatile memory of claim 11 , wherein:
the layer of undoped polysilicon is connected to the global bit line via an integrated resistor arranged between the layer of undoped polysilicon and the global bit line.
15. The non-volatile memory of claim 1 , wherein:
the non-volatile memory configured to adjust the adjustable resistance local bit line from a conducting state into a non-conducting state based on a first voltage applied to the select gate.
16. The non-volatile memory of claim 11 , wherein:
the non-volatile memory configured to adjust the layer of undoped polysilicon from a conducting state into a non-conducting state based on a first voltage applied to the select gate.