IP Library Granted Patent US 9,443,910
Granted Patent B1
US 9,443,910 · App. 14/795,211 · Granted Sep 13, 2016

Silicided bit line for reversible-resistivity memory

Inventors: Kan Fujiwara (Yokkaichi, JP); Takuya Futase (Nagoya, JP); Toshihiro Iizuka (Yokkaichi, JP); Shin Kikuchi (Nagoya, JP); Yoichiro Tanaka (Nagoya, JP); Akio Nishida (Nagoya, JP); Christopher J Petti (Mountain View, CA)
Assignee: SanDisk Technologies LLC
H01L27/2481H01L27/2436H01L45/08H01L45/12H01L45/1253H01L45/146H01L45/1608H01L21/8221H01L27/249H01L27/2454
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Quick Facts
Patent No.
US 9,443,910
App. No.
14/795,211
Granted
Sep 13, 2016
Kind
B1
Abstract

A three-dimensional (3D) non-volatile memory array having a silicide bit line and method of fabricating is disclosed. The fabrication technique may comprise forming a metal silicide for at least a portion of the bit line. The device has reversible resistivity material between the word lines and the bit lines. The reversible resistivity material may be a metal oxide. The metal that is used to form the silicide may serve as an oxygen scavenger to draw oxygen away from the silicon, thus preventing formation of silicon oxide between the reversible resistivity material and the bit line. The metal silicide may also help prevent formation of a depletion layer in silicon in the bit line.

Claims (78)

1. A method of fabricating non-volatile storage, comprising:

forming a plurality of word lines;

forming reversible resistivity material adjacent to the plurality of word lines; and

forming a plurality of bit lines that comprise a silicide, wherein the reversible resistivity material resides between the word lines and the bit lines, wherein forming the plurality of bit lines comprises:

forming a silicon region in contact with the reversible resistivity material;

forming a metal region in contact with the silicon region; and

performing a siliciding anneal after forming the metal region in contact with the silicon region.

2. The method of claim 1 , wherein forming the plurality of bit lines comprises:

forming a polycrystalline silicon region between the reversible resistivity material and the silicide.

3. The method of claim 1 , wherein forming the plurality of bit lines comprises:

forming a region of the silicide between the reversible resistivity material and a polycrystalline silicon region.

4. The method of claim 1 , wherein forming the plurality of bit lines comprises:

forming an entire bit line from the silicide.

5. The method of claim 1 , wherein forming the plurality of bit lines that comprise the silicide comprises:

forming nickel-silicide.

6. The method of claim 1 , wherein forming the plurality of bit lines that comprise the silicide comprises:

forming cobalt-silicide.

7. The method of claim 1 , wherein:

the plurality of word lines comprise titanium nitride;

the reversible resistivity material comprises a metal oxide; and

the plurality of bit lines comprise polycrystalline silicon and the silicide.

8. The method of claim 7 , wherein the polycrystalline silicon is in direct contact with the metal oxide.

9. The method of claim 1 , further comprising:

forming a plurality of global bit lines over a substrate having a major surface that extends horizontally, wherein the plurality of word lines extend horizontally with respect to the major surface of the substrate, wherein the silicide extends vertically with respect to the major surface of the substrate, wherein the plurality of bit lines extend vertically with respect to the major surface of the substrate; and

forming a plurality of select transistors over the plurality of global bit lines, wherein the plurality of select transistors reside between the plurality of global bit lines and the plurality of vertical bit lines.

10. The method of claim 1 , wherein the reversible resistivity material comprises a metal oxide.

11. A non-volatile storage system, comprising:

a plurality of word lines;

a plurality of bit lines that comprise polycrystalline silicon and a silicide; and

a reversible resistivity switching material between respective ones of the word lines and respective ones of the bit lines, a region of the polycrystalline silicon resides between the reversible resistivity switching material and a region of the silicide.

12. The non-volatile storage system of claim 11 , wherein the silicide is a metal silicide.

13. The non-volatile storage system of claim 11 , wherein the silicide is a cobalt silicide.

14. The non-volatile storage system of claim 11 , wherein the silicide is a nickel silicide.

15. The non-volatile storage system of claim 11 , wherein:

the plurality of word lines comprise titanium nitride; and

the reversible resistivity switching material comprises a metal oxide.

16. The non-volatile storage system of claim 11 , further comprising:

a substrate having a major surface that extends horizontally, wherein the plurality of word lines extend horizontally with respect to the major surface of the substrate, wherein the silicide extends vertically with respect to the major surface of the substrate, wherein the plurality of bit lines extend vertically with respect to the major surface of the substrate;

a plurality of global bit lines over the substrate; and

a plurality of select transistors that reside between the plurality of global bit lines and the plurality of vertical bit lines.

17. The non-volatile storage system of claim 11 , wherein the reversible resistivity switching material comprises a metal oxide.

18. The non-volatile storage system of claim 11 , further comprising:

a substrate; and

a monolithic three dimensional memory array comprising multiple memory levels that resides above the substrate, wherein the monolithic three dimensional memory array comprises memory cells that comprise the reversible resistivity switching material.

19. A method of fabricating a non-volatile storage device, the method comprising:

forming a plurality of global bit lines over a substrate having a major surface that extends horizontally;

forming a plurality of vertical select transistors over the plurality of global bit lines;

forming a plurality of word line layers alternating with a plurality of insulating layers over the vertical select transistors, wherein the plurality of word line layers extend horizontally with respect to the major surface of the substrate;

etching the plurality of insulating layers and the plurality of word line layers to form a plurality of stacks comprising insulating lines and word lines, the stacks having vertical sidewalls;

forming reversible resistivity material on the vertical sidewalls of the stacks, the reversible resistivity material having vertical sidewalls; and

forming vertical bit lines between the stacks, wherein forming the vertical bit lines comprises:

forming silicon on the vertical sidewalls of the reversible resistivity material, the silicon having vertical sidewalls;

forming a metal on the vertical sidewalls of the silicon;

forming a silicide from at least a portion of the silicon and at least a portion of the metal; and

removing any unreacted metal after performing the silicide.

20. The method of claim 19 , wherein the reversible resistivity material comprises a metal oxide.

21. A non-volatile storage system, comprising:

a plurality of word lines;

a plurality of bit lines that are formed entirely from a silicide; and

a reversible resistivity switching material between respective ones of the word lines and respective ones of the bit lines.

22. A non-volatile storage system, comprising:

a substrate having a major surface that extends horizontally;

a plurality of word lines that extend horizontally with respect to the major surface of the substrate;

a plurality of vertical bit lines that comprise a silicide that extends vertically with respect to the major surface of the substrate;

a reversible resistivity switching material between respective ones of the word lines and respective ones of the vertical bit lines;

a plurality of global bit lines over the substrate; and

a plurality of select transistors that reside between the plurality of global bit lines and the plurality of vertical bit lines.

23. A method of fabricating non-volatile storage, comprising:

forming a plurality of word lines;

forming reversible resistivity material adjacent to the plurality of word lines; and

forming a plurality of bit lines that comprise a silicide, wherein the reversible resistivity material resides between the word lines and the bit lines, wherein forming the plurality of bit lines comprises forming an entire bit line from the silicide.

24. A method of fabricating non-volatile storage, comprising:

forming a plurality of word lines;

forming reversible resistivity material adjacent to the plurality of word lines; and

forming a plurality of bit lines that comprise polycrystalline silicon and a silicide, wherein the polycrystalline silicon is in direct contact with the reversible resistivity material, wherein the reversible resistivity material resides between the word lines and the bit lines.

25. The method of claim 24 , wherein:

the plurality of word lines comprise titanium nitride; and

the reversible resistivity material comprises a metal oxide.

Assignments (4)
CHANGE OF NAME Recorded May 25, 2016
From: SANDISK TECHNOLOGIES INC
To: SANDISK TECHNOLOGIES LLC
Reel/Frame 038812/0954 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT LISTED PATENT NUMBER 8853569 TO THE CORRECT PATENT NUMBER 8883569 PREVIOUSLY RECORDED ON REEL 038300 FRAME 0665. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Apr 25, 2016
From: SANDISK 3D LLC
To: SANDISK TECHNOLOGIES INC.
Reel/Frame 038520/0552 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 30, 2016
From: SANDISK 3D LLC.
To: SANDISK TECHNOLOGIES INC.
Reel/Frame 038300/0665 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 9, 2015
From: FUJIWARA, KAN; FUTASE, TAKUYA; IIZUKA, TOSHIHIRO; KIKUCHI, SHIN; TANAKA, YOICHIRO; NISHIDA, AKIO; PETTI, CHRISTOPHER J
To: SANDISK 3D LLC
Reel/Frame 036050/0750 →