Monolithic three dimensional memory arrays formed using sacrificial polysilicon pillars

1. A method of forming a monolithic three-dimensional memory array, the method comprising:

forming a first vertically-oriented polysilicon pillar above a substrate, the first vertically-oriented polysilicon pillar surrounded by a dielectric material;

forming a first gate dielectric material on a sidewall of the first vertically-oriented polysilicon pillar;

forming a first gate electrode on a sidewall of the first gate dielectric material;

removing the first vertically-oriented polysilicon pillar and the first gate dielectric material to form a first void in the dielectric material; and

filling the first void with a conductive material to form a first via, wherein the conductive material is coupled to the first gate electrode.

2. The method of claim 1 , wherein the first vertically-oriented polysilicon pillar comprises a first region, a second region and a third region.

3. The method of claim 2 , wherein the first region comprises n+ polysilicon, the second region comprises p+ polysilicon, and the third region comprises n+ polysilicon.

4. The method of claim 2 , wherein the first region comprises p+ polysilicon, the second region comprises n+ polysilicon, and the third region comprises p+ polysilicon.

5. The method of claim 1 , further comprising:

forming a second vertically-oriented polysilicon pillar above the substrate, the second vertically-oriented polysilicon pillar surrounded by the dielectric material;

forming a second gate dielectric material on a sidewall of the second vertically-oriented polysilicon pillar;

forming a second gate electrode on a sidewall of the second gate dielectric material;

removing the second vertically-oriented polysilicon pillar and the second gate dielectric material to form a second void in the dielectric material; and

filling the second void with the conductive material to form a second via, wherein the conductive material is coupled to the second gate electrode.

6. The method of claim 5 , wherein the second vertically-oriented polysilicon pillar comprises a first region, a second region and a third region.

7. The method of claim 6 , wherein the first region comprises n+ polysilicon, the second region comprises p+ polysilicon, and the third region comprises n+ polysilicon.

8. The method of claim 6 , wherein the first region comprises p+ polysilicon, the second region comprises n+ polysilicon, and the third region comprises p+ polysilicon.

9. The method of claim 5 , further comprising:

forming a row select line comprising a first portion and a second portion, the first portion of the row select line separated from the second portion of the row select line by a distance; and

coupling the first portion of the row select line to the first via and coupling the second portion of the row select line to the second via.

10. The method of claim 9 , wherein the distance is between about 4500 angstroms and about 27000 angstroms.

11. A method comprising:

forming a plurality of vertically-oriented polysilicon pillars above a substrate, each of the plurality of vertically-oriented polysilicon pillars surrounded by a dielectric material, the plurality of vertically-oriented polysilicon pillars comprising a first vertically-oriented polysilicon pillar and a second vertically-oriented polysilicon pillar;

disposing a row select line adjacent the first vertically-oriented polysilicon pillar;

removing the second vertically-oriented polysilicon pillar to form a void in the dielectric material;

filling the void with a conductive material to form a first via; and

coupling the row select line to the via.

12. The method of claim 11 , wherein each of the plurality of vertically-oriented polysilicon pillars comprises a first region, a second region and a third region.

13. The method of claim 12 , wherein the first region comprises n+ polysilicon, the second region comprises p+ polysilicon, and the third region comprises n+ polysilicon.

14. The method of claim 12 , wherein the first region comprises p+ polysilicon, the second region comprises n+ polysilicon, and the third region comprises p+ polysilicon.

15. The method of claim 11 , further comprising disposing a gate dielectric layer between the row select line and the first vertically-oriented polysilicon pillar.

16. A method of forming a row select line for a monolithic three-dimensional memory array, method comprising:

forming a first portion of the row select line and a second portion of the row select line, the first portion of the row select line separated from the second portion of the row select line by a distance;

forming a first via and a second via by:

forming a first vertically-oriented polysilicon pillar and a second vertically-oriented polysilicon pillar above a substrate, each of the first vertically-oriented polysilicon pillar and the second vertically-oriented polysilicon pillar surrounded by a dielectric material;

removing the first vertically-oriented polysilicon pillar to form a first void in the dielectric material;

removing the second vertically-oriented polysilicon pillar to form a second void in the dielectric material; and

filling the first void with a conductive material to form a first via and filling the second void with the conductive material to form a second via;

coupling the first portion of the row select line to the first via; and

coupling the second portion of the row select line to the second via.

17. The method of claim 16 , wherein each of the first vertically-oriented polysilicon pillar and the second vertically-oriented polysilicon pillar comprises a first region, a second region and a third region.

18. The method of claim 17 , wherein the first region comprises n+ polysilicon, the second region comprises p+ polysilicon, and the third region comprises n+ polysilicon.

19. The method of claim 17 , wherein the first region comprises p+ polysilicon, the second region comprises n+ polysilicon, and the third region comprises p+ polysilicon.

20. The method of claim 16 , further comprising forming a conductive trace coupling the first via and the second via.