Charge pump with a power-controlled clock buffer to reduce power consumption and output voltage ripple
A charge pump system includes a charge pump that receives its clock signals, generated by an oscillator circuit, though a clock buffer. The clock buffer is power-controlled to reduce power consumption and output voltage ripple. The buffer is formed of a series of inverter that are connected to the power supply level through a clamping element, such as a transistor whose gate is controlled by a regulation signal based on feedback from the pump's output.
1. A monolithic three-dimensional semiconductor memory device, said memory device comprising:
a plurality of memory device levels vertically disposed above a substrate wherein said memory device levels have a plurality of non-volatile memory elements;
said memory elements in a memory device level being horizontally separated from each other and arranged in two or more horizontal rows of two or more memory elements;
at least one of said memory device levels having memory elements substantially vertically aligned with memory elements of a vertically adjacent memory device level;
at least one word line being common among at least two memory elements in one of said horizontal rows in one of said memory device levels; and
a charge pump system connectable to provide an output voltage to one or more of said memory elements for use in the operation thereof, the charge pump system comprising:
a charge pump circuit connected to receive N pump clock signals and generate therefrom the output voltage, where N is an integer greater than or equal to one;
regulation circuitry connected to receive the output voltage and generate a regulation signal based on the output voltage;
an oscillator circuit providing N initial clock signals; and
N clock buffer circuits, each receiving a corresponding one of the initial clock signals and generating therefrom a corresponding one of the pump clock signals, wherein each of the buffer circuits includes:
a plurality of inverters connected in series, with the first inverter in the series connected to receive the corresponding initial clock signal as input and the last inverter in the series providing the corresponding pump clock signal as output; and
a corresponding plurality of clamp elements connected to receive the regulation signal and through which a corresponding one of the inverters is connected to a power supply level, the voltage level being supplied to the corresponding inverter being dependent upon the regulation signal.
2. The monolithic three-dimensional semiconductor memory device of claim 1 , wherein the charge pump circuit is a Dickson type charge pump.
3. The monolithic three-dimensional semiconductor memory device of claim 1 , wherein the charge pump circuits is a voltage doubler type charge pump.
4. The monolithic three-dimensional semiconductor memory device of claim 1 , wherein the charge pump circuit is a four-phase type of charge pump.
5. The monolithic three-dimensional semiconductor memory device of claim 1 , wherein N is two and the pump clock signals are non-overlapping.
6. The monolithic three-dimensional semiconductor memory device of claim 1 , wherein the regulation circuitry includes:
a voltage divider connected between the output voltage and ground; and
a comparator having a first input connected to a node of the voltage divider, a second input connected to a reference voltage level, and an output supplying the regulation signal.
7. The monolithic three-dimensional semiconductor memory device of claim 1 , wherein each of the inverters comprises:
a PMOS transistor between an internal node and, through the corresponding clamp element, the power supply level; and
an NMOS transistor connected between the internal node and ground,
wherein the input of the inverter is connected to the gates of the PMOS and NMOS transistors and the output of the inverter is taken from the internal node.
8. The monolithic three-dimensional semiconductor memory device of claim 1 , wherein the clamp element is a PMOS transistor having a gate voltage determined by the regulation signal.
9. The monolithic three-dimensional semiconductor memory device of claim 1 , wherein the clamp element is an NMOS transistor having a gate voltage determined by the regulation signal.
10. The monolithic three-dimensional semiconductor memory device of claim 9 , wherein the regulation circuitry includes an auxiliary charge pump for use in generating the regulation signal.
11. The monolithic three-dimensional semiconductor memory device of claim 1 , wherein the clamp element is a PMOS transistor having a gate voltage determined by the regulation signal in parallel with an NMOS transistor having a gate voltage determined by the regulation signal.
12. The monolithic three-dimensional semiconductor memory device of claim 1 , wherein the output voltage is a write voltage level.
13. The monolithic three-dimensional semiconductor memory device of claim 1 , wherein the output voltage is an erase voltage level.