Methods and apparatus for vertical cross point re-RAM array bias calibration

1. A method comprising:

determining bias voltages for a non-volatile storage system comprising a plurality of bit lines, first and second word line combs, each word line comb comprising a plurality of word lines, a plurality of memory elements, each memory element coupled between one of the bit lines and one of the word lines, a first memory element coupled between the one of the bit lines and a word line of the second word line comb, and a second memory element coupled between a word line of the first word line comb and a second one of the bit lines, by:

estimating a data pattern previously stored in a plurality of memory elements coupled to the first word line comb; and

determining a first bias voltage of one of the bit lines and a second bias voltage of the second word line comb based on the estimate of the previously stored data pattern for a predetermined bias voltage for the first word line comb,

wherein the first bias voltage and the second bias voltage are determined such that a first voltage across the first memory element substantially balances a second voltage across the second memory element.

2. The method of claim 1 , wherein estimating comprises:

biasing the first word line comb to a first voltage;

biasing the second word line comb to a second voltage;

biasing the plurality of bit lines coupled to the first word line comb to a third voltage; and

measuring a current conducted by the first word line comb.

3. The method of claim 2 , wherein:

biasing the plurality of bit lines coupled to the first word line comb comprises coupling the plurality of bit lines coupled to the first word line comb to a driver circuit; and

measuring a current conducted by the first word line comb comprises measuring a current conducted by the driver circuit.

4. The method of claim 1 , wherein estimating comprises:

biasing the first word line comb to a first voltage;

biasing the second word line comb to a second voltage;

floating the plurality of bit lines coupled to the first word line comb; and

measuring a current conducted by the first word line comb.

5. The method of claim 4 , wherein:

biasing the first word line comb comprises coupling the first word line comb to a driver circuit; and

measuring a current conducted by the first word line comb comprises measuring a current conducted by the driver circuit.

6. The method of claim 4 , wherein:

biasing the second word line comb comprises coupling the second word line comb to a driver circuit; and

measuring a current conducted by the first word line comb comprises measuring a current conducted by the driver circuit.

7. The method of claim 1 , wherein the first memory element and the second memory element are unselected memory elements.

8. An apparatus comprising:

a plurality of bit lines;

first and second word line combs, each word line comb comprising a plurality of word lines;

a plurality of memory elements, each coupled between one of the bit lines and one of the word lines;

a first memory element coupled between the one of the bit lines and a word line of the second word line comb;

a second memory element coupled between a word line of the first word line comb and a second one of the bit lines; and

a memory controller configured to:

measure a total current conducted by the first word line comb;

estimate a data pattern of a plurality of memory elements coupled to the first word line comb based on the measured current; and

determine, for a predetermined bias voltage for the first word line comb, a first bias voltage of one of the bit lines and a second bias voltage of the second word line comb based on the estimated data pattern, such that a first voltage across the first memory element substantially balances a second voltage across the second memory element.

9. The apparatus of claim 8 , wherein:

the memory controller is further configured to:

bias the first word line comb to a first voltage;

bias the second word line comb to a second voltage; and

couple a driver circuit to bias the plurality of bit lines coupled to the first word line comb to a third voltage; and

measuring a current conducted by the first word line comb comprises measuring a current conducted by the driver circuit.

10. The apparatus of claim 8 , wherein:

the memory controller is further configured to:

couple a first driver circuit to bias the first word line comb to a first voltage;

couple a second driver circuit to bias the second word line comb to a second voltage; and

float the plurality of bit lines coupled to the first word line comb; and

measuring a current conducted by the first word line comb comprises measuring a current conducted by the first driver circuit or the second driver circuit.

11. The apparatus of claim 8 , wherein the first memory element and the second memory element are unselected memory elements.

12. The apparatus of claim 8 , wherein the memory controller is further configured to:

perform a read operation of a plurality of memory elements coupled to a word line of the first word line comb;

determine a count of a number of the plurality of memory elements coupled to a word line of the first word line comb having a predetermined data state; and

determine the first bias voltage and the second bias voltage based on the determined count.

13. A non-volatile storage system, comprising:

a memory array comprising a plurality of bit lines, first and second word line combs, each word line comb comprising a plurality of word lines, a plurality of memory elements, each memory element coupled between one of the bit lines and one of the word lines, a first memory element coupled between the one of the bit lines and a word line of the second word line comb, and a second memory element coupled between a word line of the first word line comb and a second one of the bit lines; and

a managing circuit in communication with the memory array, the managing circuit configured to:

estimate a data pattern previously stored in a plurality of memory elements coupled to the first word line comb; and

determine a first bias voltage of one of the bit lines and a second bias voltage of the second word line comb based on the estimated data pattern for a predetermined bias voltage for the first word line comb, such that a first voltage across the first memory element substantially balances a second voltage across the second memory element.

14. The non-volatile storage system of claim 13 , wherein the managing circuit is further configured to:

bias the first word line comb to a first voltage;

bias the second word line comb to a second voltage;

bias the plurality of bit lines coupled to the first word line comb to a third voltage; and

measure a current conducted by the first word line comb.

15. The non-volatile storage system of claim 14 , wherein:

biasing the plurality of bit lines comprises coupling a driver circuit to the plurality of bit lines coupled to the first word line comb; and

measuring a current conducted by the first word line comb comprises measuring a current conducted by the driver circuit.

16. The non-volatile storage system of claim 13 , wherein the managing circuit is further configured to:

bias the first word line comb to a first voltage;

bias the second word line comb to a second voltage;

float the plurality of bit lines coupled to the first word line comb; and

measure a current conducted by the first word line comb.

17. The non-volatile storage system of claim 16 , wherein:

biasing the first word line comb comprises coupling the first word line comb to a driver circuit; and

measuring a current conducted by the first word line comb comprises measuring a current conducted by the driver circuit.

18. The non-volatile storage system of claim 16 , wherein:

biasing the second word line comb comprises coupling the second word line comb to a driver circuit; and

measuring a current conducted by the first word line comb comprises measuring a current conducted by the driver circuit.