Resistive random access memory containing a steering element and a tunneling dielectric element

1. A memory device comprising:

a substrate;

an alternating stack of insulating layers and conductive material layers that alternate along a first direction on the side of the alternating stack that is perpendicular to a top surface of the substrate;

an electrically conductive line that extends along the first direction; and

at least one memory cell, the at least one memory cell comprising:

a steering element;

a resistive memory element; and

a tunneling dielectric element located between the steering element and the resistive memory element.

2. The memory device of claim 1 , wherein:

the steering element comprises a diode;

a predominant mode of electrical current conduction through the tunneling dielectric element is charge carrier tunneling; and

the resistive memory element has multiple states providing different electrical resistance depending on an electrical bias that is previously applied thereto.

3. The memory device of claim 2 , wherein the diode comprises:

an n-doped semiconductor region including n-type dopants at an atomic concentration greater than 5.0 ×10 19 /cm 3 ; and

a p-doped semiconductor region including p-type dopants at an atomic concentration less than 5.0 ×10 19 /cm 3 .

4. The memory device of claim 3 , wherein the tunneling dielectric element contacts the p-doped semiconductor region of the diode.

5. The memory device of claim 4 , wherein during an application of a reverse bias to the memory cell, holes accumulate in the p-type semiconductor region of the diode adjacent to the tunneling dielectric element to facilitate electron tunneling from the resistive memory element to the n-type semiconductor region of the diode through the tunneling dielectric element and the p-type semiconductor region of the diode.

6. The memory device of claim 1 , wherein the tunneling dielectric element comprises a dielectric material having a dielectric constant of at least 7.0 and the resistive memory element comprises a dielectric oxide providing a reduction in resistivity upon formation of conductive filaments therein.

7. The memory device of claim 6 , wherein the tunneling dielectric element comprises a dielectric material selected from silicon nitride and aluminum oxide which does not form conductive filaments therein upon application of a bias thereto.

8. The memory device of claim 1 , wherein the tunneling dielectric element has a thickness in a range from 0.6 nm to 4 nm.

9. The memory device of claim 1 , wherein the resistive memory element comprises a dielectric oxide of a metal selected from Hf, Ti, Zr, and Ta.

10. The memory device of claim 1 , wherein:

each of the conductive material layers comprises a word line;

the electrically conductive line comprises a bit line;

one of the word line or the bit line is in contact with the steering element; and

another one of the word line or the bit line is in contact with the resistive memory element.

11. The memory device of claim 10 , wherein:

the bit line extends along the first direction and is separated from the alternating stack along a second direction; and

a plurality of the resistive memory elements are located at each level of the word lines.

12. The memory device of claim 11 , wherein:

the resistive memory elements in the respective memory elements comprise discrete portions of a dielectric metal oxide disposed between neighboring pairs of the insulating layer and the word line; and

each resistive memory element comprises a pair of parallel portions adjoined by a connecting portion which surround the word line on three sides.

13. The memory device of claim 12 , wherein:

the tunneling dielectric elements comprise discrete portions of a dielectric material having a dielectric constant of at least 7.0; and

each tunneling dielectric element comprises a pair of parallel portions adjoined by a connecting portion, which surround the resistive memory element and the word line on three sides.

14. The memory device of claim 11 , wherein the steering elements in the plurality of memory elements comprise portions of a single p-n junction within a layer stack including a p-doped semiconductor layer and an n-doped semiconductor layer, the portions of the layer stack being spaced from one another along the first direction.

15. The memory device of claim 11 , wherein the steering elements in the plurality of memory elements comprise a plurality of discrete p-n junctions located at each level of the word lines and spaced from one another along the first direction.

16. The memory device of claim 11 , wherein:

the bit line comprises a doped semiconductor layer having a doping of a first conductivity type; and

each steering element in the plurality of memory elements comprise a diode including a portion of the doped semiconductor layer and a plurality of doped semiconductor portions located at each level of the word lines and having a doping of a second conductivity type that is the opposite of the first conductivity type.

17. The memory device of claim 11 , wherein:

the resistive memory elements in the plurality of memory elements comprise portions of a dielectric material layer extending along the first direction, the portions of the dielectric material layer being spaced from one another along the first direction; and

the tunneling dielectric elements in the plurality of memory elements comprise portions of a tunneling dielectric layer extending along the first direction, the portions of the tunneling dielectric layer being spaced along the first direction.

18. The memory device of claim 17 , wherein:

the word lines comprise doped semiconductor layers having a doping of a first conductivity type; and

a doped semiconductor material layer extending along the first direction and having a doping of a second conductivity type that is the opposite of the first conductivity type contacts each of the insulating layers and word lines.

19. The memory device of claim 11 , wherein:

the steering element comprises a diode;

the tunneling dielectric element comprises a dielectric material having a dielectric constant of at least 7.0;

the tunneling dielectric element has a thickness in a range from 0.6 nm to 4 nm; and

each of the resistive memory elements comprises a dielectric oxide providing a reduction in resistivity upon formation of conductive filaments therein.