Monolithic three dimensional memory arrays with staggered vertical bit lines and dual-gate bit line select transistors
A monolithic three-dimensional memory array is provided that includes global bit lines disposed above a substrate, each global bit line having a long axis, vertically-oriented bit lines disposed above the global bit lines, word lines disposed above the global bit lines, memory cells coupled between the vertically-oriented bit lines and the word lines, and vertically-oriented bit line select transistors coupled between the vertically-oriented bit lines and the global bit lines. Each vertically-oriented bit line select transistor has a width, a first control terminal and a second control terminal. The word lines and the vertically-oriented bit lines have a half-pitch, and the width of the vertically-oriented bit line select transistors is between about two times the half-pitch and about three times the half-pitch. Vertical bit lines disposed above adjacent global bit lines are offset from one another in a direction along the long axis of the global bit lines.
1. A monolithic three-dimensional memory array comprising:
a plurality of global bit lines disposed above a substrate, each global bit line extending in a first direction, the plurality of global bit lines arranged in a second direction perpendicular to the first direction;
a plurality of vertically-oriented bit lines disposed above the global bit lines, each of the vertically-oriented bit lines extending in a third direction perpendicular to the first and second directions;
a plurality of word lines disposed above the global bit lines;
a plurality of memory cells coupled between the vertically-oriented bit lines and the word lines; and
a plurality of vertically-oriented bit line select transistors coupled between the vertically-oriented bit lines and the global bit lines, each vertically-oriented bit line select transistor comprising a width in the second direction, a first control terminal and a second control terminal,
wherein:
the word lines and the vertically-oriented bit lines have a half-pitch, and the width of each vertically-oriented bit line select transistor is between about two times the half-pitch and about three times the half-pitch, and
vertically-oriented bit lines disposed above adjacent global bit lines are offset from one another in the first direction.
2. The monolithic three-dimensional memory array of claim 1 , wherein the vertically-oriented bit line select transistors comprise field effect transistors.
3. The monolithic three-dimensional memory array of claim 1 , wherein:
the vertically-oriented bit line select transistors comprise field effect transistors;
the first control terminal comprises a first gate terminal; and
the second control terminal comprises a second gate terminal.
4. The monolithic three-dimensional memory array of claim 1 , wherein the first control terminal and the second control terminal of each vertically-oriented bit line select transistor are disposed on opposite sides of the vertically-oriented transistor.
5. The monolithic three-dimensional memory array of claim 1 , wherein each vertically-oriented bit line select transistor comprises a first terminal and a second terminal, and the first control terminal may be used to selectively induce a first conductive channel between the first terminal and the second terminal, and the second control terminal may be used to selectively induce a second conductive channel between the first terminal and the second terminal.
6. The monolithic three-dimensional memory array of claim 1 , wherein the first control terminal and the second control terminal of each vertically-oriented bit line select transistor may be used to individually and collectively turn ON the vertically-oriented bit line select transistor.
7. The monolithic three-dimensional memory array of claim 1 , wherein the vertically-oriented bit line select transistors comprise vertically-oriented pillar-shaped transistors.
8. The monolithic three-dimensional memory array of claim 1 , wherein the memory cells comprise reversible resistance-switching memory cells.
9. The monolithic three-dimensional memory array of claim 1 , further comprising a plurality of row select lines coupled to the first control terminal and the second control terminal of each vertically-oriented bit line select transistor.
10. A method comprising:
providing a monolithic three-dimensional memory array that includes a plurality of global bit lines disposed above a substrate, each global bit line extending in a first direction, the plurality of global bit lines arranged in a second direction perpendicular to the first direction, a plurality of vertically-oriented bit lines disposed above the global bit lines, each of the vertically-oriented bit lines extending in a third direction perpendicular to the first and second directions, with vertically-oriented bit lines disposed above adjacent global bit lines offset from one another in the first direction, a plurality of word lines disposed above the global bit lines, a plurality of memory cells coupled between the vertically-oriented bit lines and the word lines, and a plurality of vertically-oriented bit line select transistors coupled between the vertically-oriented bit lines and the global bit lines, each vertically-oriented bit line select transistor comprising a width in the second direction, a first control terminal and a second control terminal, the word lines and the vertically-oriented bit lines having a half-pitch, and the width of each vertically-oriented bit line select transistor is between about two times the half-pitch and about three times the half-pitch;
in a first mode of operation, using one of the first control terminal or the second control terminal of a particular vertically-oriented bit line select transistors to turn ON the particular vertically-oriented bit line select transistor; and
in a second mode of operation, using both the first control terminal and the second control terminal of the particular vertically-oriented bit line select transistors to turn ON the particular vertically-oriented bit line select transistor.
11. The method of claim 10 , wherein the first mode of operation comprises a read operation, and the second mode of operation comprises a write operation.
12. The method of claim 10 , further comprising:
in the first mode of operation, determining a data state of a memory cell coupled to the particular vertically-oriented bit line select transistor; and
in the second mode of operation, changing a data state of the memory cell coupled to the particular vertically-oriented bit line select transistor.
13. The method of claim 10 , wherein:
the vertically-oriented bit line select transistors comprise field effect transistors;
the first control terminal comprises a first gate terminal; and
the second control terminal comprises a second gate terminal.
14. The method of claim 10 , wherein each vertically-oriented bit line select transistor comprises a first terminal and a second terminal, and the method further comprises:
using the first control terminal of the particular vertically-oriented bit line select transistor to selectively induce a first conductive channel between the first terminal and the second terminal of the particular vertically-oriented bit line select transistor; and
using the second control terminal of the particular vertically-oriented bit line select transistor to selectively induce a second conductive channel between the first terminal and the second terminal of the particular vertically-oriented bit line select transistor.
15. A method of providing a monolithic three-dimensional memory array, the method comprising:
providing a plurality of global bit lines above a substrate, each global bit line extending in a first direction, the plurality of global bit lines arranged in a second direction perpendicular to the first direction;
providing a plurality of vertically-oriented bit lines above the global bit lines, each of the vertically-oriented bit lines extending in a third direction perpendicular to the first and second directions, each of the vertically-oriented bit lines having a half-pitch;
providing a plurality of word lines above the global bit lines, each of the word lines having the half-pitch;
coupling a plurality of memory cells between the vertically-oriented bit lines and the word lines;
coupling a plurality of vertically-oriented bit line select transistors between the vertically-oriented bit lines and the global bit lines, each vertically-oriented bit line select transistor comprising a width in the second direction, a first control terminal and a second control terminal; and
offsetting vertically-oriented bit lines disposed above adjacent global bit lines from one another in the first direction.
16. The method of claim 15 , wherein:
the vertically-oriented bit line select transistors comprise field effect transistors;
the first control terminal comprises a first gate terminal; and
the second control terminal comprises a second gate terminal.
17. The method of claim 15 , further comprising disposing the first control terminal and the second control terminal of each vertically-oriented bit line select transistor on opposite sides of the vertically-oriented transistor.
18. The method of claim 15 , wherein the vertically-oriented bit line select transistors comprise vertically-oriented pillar-shaped transistors.
19. The method of claim 15 , wherein the memory cells comprise reversible resistance-switching memory cells.
20. The method of claim 15 , further comprising coupling a plurality of row select lines the first control terminal and the second control terminal of each vertically-oriented bit line select transistor.