ReRAM MIM structure formation
Methods for improving the operation of a memory array by arranging a Metal-Insulator-Metal (MIM) structure between a word line and an adjustable resistance bit line structure are described. The MIM structure may correspond with a metal/ReRAM material/metal structure that is arranged between the word line and an intrinsic polysilicon region of the adjustable resistance bit line structure. In one example, a word line (e.g., TiN) may be arranged adjacent to a ReRAM material (e.g., HfOx) that is adjacent to a first metal (e.g., TiN) that is adjacent to the intrinsic polysilicon region. The first metal may comprise a metal, metal-nitride, or a metal-silicide. In another example, the word line may be arranged adjacent to a ReRAM material that is adjacent to a first metal (e.g., TiN) that is adjacent to a second metal different from the first metal (e.g., tungsten) that is adjacent to the intrinsic polysilicon region.
1. A non-volatile storage system, comprising:
a first word line;
an adjustable resistance bit line structure including an adjustable resistance local bit line and a select gate that is electrically isolated from the adjustable resistance local bit line by a dielectric layer; and
a first memory element arranged between the first word line and a first layer of metal in a first dimension, the first layer of metal is arranged between the first memory element and a second layer of metal different from the first layer of metal in the first dimension, the second layer of metal is arranged between the first layer of metal and the adjustable resistance local bit line in the first dimension, the adjustable resistance bit line structure configured to adjust a resistance of the adjustable resistance local bit line from a high off-resistance to a low on-resistance based on a first voltage applied to the select gate.
2. The non-volatile storage system of claim 1 , wherein:
the first layer of metal comprises one of a metal, a metal-nitride, or a metal-silicide.
3. The non-volatile storage system of claim 1 , wherein:
the first layer of metal comprises TiN.
4. The non-volatile storage system of claim 1 , wherein:
the second layer of metal comprises tungsten.
5. The non-volatile storage system of claim 1 , wherein:
the first memory element directly abuts the first layer of metal, the first layer of metal directly abuts the second layer of metal, the second layer of metal directly abuts the adjustable resistance local bit line.
6. The non-volatile storage system of claim 1 , wherein:
the adjustable resistance bit line structure is configured to set the adjustable resistance local bit line into either a conducting state or a non-conducting state based on the first voltage applied to the select gate.
7. The non-volatile storage system of claim 1 , wherein:
the adjustable resistance local bit line comprises undoped polysilicon.
8. The non-volatile storage system of claim 1 , wherein:
the adjustable resistance bit line structure includes the dielectric layer arranged between the select gate and the adjustable resistance local bit line in the first dimension.
9. The non-volatile storage system of claim 1 , wherein:
the first memory element includes a resistive random-access memory material.
10. The non-volatile storage system of claim 1 , wherein:
the first memory element is part of a memory array, the memory array comprises a three-dimensional memory array.
11. The non-volatile storage system of claim 1 , wherein:
the first memory element is part of a memory array, the memory array comprises a non-volatile memory that is monolithically formed in one or more physical levels of memory cells having active areas disposed above a silicon substrate.
12. A non-volatile memory, comprising:
a word line;
a bit line structure including a layer of intrinsic polysilicon and a select gate that is electrically isolated from the layer of intrinsic polysilicon by a dielectric layer; and
a memory element directly connected to the word line and directly connected to a layer of metal, the memory element arranged between the word line and the layer of metal in a first dimension, the layer of metal is arranged between the memory element and a second layer of metal different from the layer of metal in the first dimension, the second layer of metal is arranged between the layer of metal and the layer of intrinsic polysilicon in the first dimension, the bit line structure configured to adjust a resistance of the layer of intrinsic polysilicon from a high off-resistance to a low on-resistance based on a voltage applied to the select gate.
13. The non-volatile memory of claim 12 , wherein:
the layer of metal comprises one of a metal, a metal-nitride, or a metal-silicide.
14. The non-volatile memory of claim 12 , wherein:
the second layer of metal comprises tungsten.
15. The non-volatile memory of claim 12 , wherein:
the memory element directly abuts the layer of metal, the layer of metal directly abuts the second layer of metal, the second layer of metal directly abuts the layer of intrinsic polysilicon.
16. The non-volatile memory of claim 12 , wherein:
the layer of metal comprises titanium nitride; and
the memory element includes a resistive random-access memory material.
17. The non-volatile memory of claim 12 , wherein:
the bit line structure includes the dielectric layer arranged between the select gate and the layer of intrinsic polysilicon in the first dimension; and
the bit line structure configured to set the layer of intrinsic polysilicon into either a conducting state or a non-conducting state based on the voltage applied to the select gate.