Patent Assignment
Reel/Frame 058871/0928
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded: 2021-11-12
Received: 2021-11-12
Pages: 15
Assignor
SANDISK TECHNOLOGIES LLC
Executed: 2021-07-29
Assignee
WODEN TECHNOLOGIES INC.
251 LITTLE FALLS DRIVE, WILMINGTON, DE, 19808, UNITED STATES
Covered Applications
(100)
DENSE ARRAYS AND CHARGE STORAGE DEVICES
App. No. 16/851,282
→
DISPLAY DEVICE WITH GRAPHICAL USER INTERFACE
App. No. 29/685,029
→
DENSE ARRAYS AND CHARGE STORAGE DEVICES
App. No. 15/971,293
→
RESONANT IGNITION CIRCUIT
App. No. 15/674,221
→
DENSE ARRAYS AND CHARGE STORAGE DEVICES
App. No. 15/368,396
→
DENSE ARRAYS AND CHARGE STORAGE DEVICES
App. No. 14/856,131
→
FAST AND STABLE ULTRA LOW DROP-OUT (LDO) VOLTAGE CLAMP DEVICE
App. No. 14/855,033
→
Regrouping and Skipping Cycles in Non-Volatile Memory
App. No. 14/515,387
→
DENSE ARRAYS AND CHARGE STORAGE DEVICES
App. No. 14/494,320
→
LOW COMPLEXITY PARTIAL PARALLEL ARCHITECTURES FOR FOURIER TRANSFORM AND INVERSE FOURIER TRANSFORM OVER SUBFIELDS OF A FINITE FIELD
App. No. 14/258,679
→
METHODS AND DEVICES FOR FORMING NANOSTRUCTURE MONOLAYERS AND DEVICES INCLUDING SUCH MONOLAYERS
App. No. 14/251,092
→
DENSE ARRAYS AND CHARGE STORAGE DEVICES
App. No. 14/227,644
→
DENSE ARRAYS AND CHARGE STORAGE DEVICES
App. No. 14/227,425
→
NONVOLATILE MEMORY CELL WITHOUT A DIELECTRIC ANTIFUSE HAVING HIGH- AND LOW-IMPEDANCE STATES
App. No. 14/145,614
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METHOD OF FABRICATING A SELF-ALIGNING DAMASCENE MEMORY STRUCTURE
App. No. 14/140,468
→
METHODS AND DEVICES FOR FORMING NANOSTRUCTURE MONOLAYERS AND DEVICES INCLUDING SUCH MONOLAYERS
App. No. 14/032,548
→
Triple Patterning NAND Flash Memory
App. No. 14/018,236
→
Triple Patterning NAND Flash Memory with SOC
App. No. 14/018,163
→
COMPOSITIONS AND METHODS FOR MODULATION OF NANOSTRUCTURE ENERGY LEVELS
App. No. 14/018,260
→
Triple Patterning NAND Flash Memory with Stepped Mandrel
App. No. 14/018,258
→
METHODS AND DEVICES FOR FORMING NANOSTRUCTURE MONOLAYERS AND DEVICES INCLUDING SUCH MONOLAYERS
App. No. 13/956,483
→
METHOD FOR REDUCING DIELECTRIC OVERETCH WHEN MAKING CONTACT TO CONDUCTIVE FEATURES
App. No. 13/938,975
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APPARATUS FOR FORMING MEMORY LINES AND VIAS IN THREE DIMENSIONAL MEMORY ARRAYS USING DUAL DAMASCENE PROCESS AND IMPRINT LITHOGRAPHY
App. No. 13/911,294
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METHOD OF INHIBITING WIRE COLLAPSE
App. No. 13/862,222
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METHOD OF FABRICATING A SELF-ALIGNING DAMASCENE MEMORY STRUCTURE
App. No. 13/781,983
→
METHODS FOR INCREASED ARRAY FEATURE DENSITY
App. No. 13/760,877
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RESIST FEATURE AND REMOVABLE SPACER PITCH DOUBLING PATTERNING METHOD FOR PILLAR STRUCTURES
App. No. 13/744,971
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METHOD OF FORMING CRACK FREE GAP FILL
App. No. 13/742,239
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DENSE ARRAYS AND CHARGE STORAGE DEVICES
App. No. 13/468,731
→
SYSTEM FOR SEPARATING A DICED SEMICONDUCTOR DIE FROM A DIE ATTACH TAPE
App. No. 13/398,647
→
METHODS FOR INCREASED ARRAY FEATURE DENSITY
App. No. 13/366,916
→
THREE-DIMENSIONAL MEMORY DEVICE INCORPORATING SEGMENTED ARRAY LINE MEMORY ARRAY
App. No. 13/348,336
→
Startup Circuit and Input Capacitor Balancing Circuit
App. No. 13/347,616
→
RESIST FEATURE AND REMOVABLE SPACER PITCH DOUBLING PATTERNING METHOD FOR PILLAR STRUCTURES
App. No. 13/331,267
→
SEMICONDUCTOR DIE HAVING A REDISTRIBUTION LAYER
App. No. 13/103,792
→
METHODS AND DEVICES FOR FORMING NANOSTRUCTURE MONOLAYERS AND DEVICES INCLUDING SUCH MONOLAYERS
App. No. 13/098,082
→
METHOD FOR REDUCING DIELECTRIC OVERETCH WHEN MAKING CONTACT TO CONDUCTIVE FEATURES
App. No. 13/087,646
→
DENSE ARRAYS AND CHARGE STORAGE DEVICES
App. No. 13/027,113
→
METHOD FOR ANGULAR DOPING OF SOURCE AND DRAIN REGIONS FOR ODD AND EVEN NAND BLOCKS
App. No. 13/024,663
→
METHOD FOR FORMING DOPED POLYSILICON VIA CONNECTING POLYSILICON LAYERS
App. No. 12/897,696
→
SEMICONDUCTOR DIE HAVING A REDISTRIBUTION LAYER
App. No. 12/843,279
→
METHOD FOR ANGULAR DOPING OF SOURCE AND DRAIN REGIONS FOR ODD AND EVEN NAND BLOCKS
App. No. 12/835,468
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METHODS AND DEVICES FOR FORMING NANOSTRUCTURE MONOLAYERS AND DEVICES INCLUDING SUCH MONOLAYERS
App. No. 12/803,568
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CORRUGATED DIE EDGE FOR STACKED DIE SEMICONDUCTOR PACKAGE
App. No. 12/825,617
→
SPACER PATTERNS USING ASSIST LAYER FOR HIGH DENSITY SEMICONDUCTOR DEVICES
App. No. 12/791,103
→
METHODS FOR INCREASED ARRAY FEATURE DENSITY
App. No. 12/754,602
→
MEMORY CELL THAT INCLUDES A CARBON-BASED MEMORY ELEMENT AND METHODS OF FORMING THE SAME
App. No. 12/717,457
→
SYSTEM FOR SEPARATING A DICED SEMICONDUCTOR DIE FROM A DIE ATTACH TAPE
App. No. 12/709,952
→
METHOD OF FABRICATING A SELF-ALIGNING DAMASCENE MEMORY STRUCTURE
App. No. 12/611,087
→
NON-VOLATILE MEMORY WITH LINEAR ESTIMATION OF INITIAL PROGRAMMING VOLTAGE
App. No. 12/573,405
→
METHOD FOR FORMING DOPED POLYSILICON VIA CONNECTING POLYSILICON LAYERS
App. No. 12/489,214
→
PATTERNING OF SUBMICRON PILLARS IN A MEMORY ARRAY
App. No. 12/422,072
→
METHOD FOR ANGULAR DOPING OF SOURCE AND DRAIN REGIONS FOR ODD AND EVEN NAND BLOCKS
App. No. 12/419,637
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MEMORY CELL THAT EMPLOYS A SELECTIVELY FABRICATED CARBON NANO-TUBE REVERSIBLE RESISTANCE-SWITCHING ELEMENT FORMED OVER A BOTTOM CONDUCTOR AND METHODS OF FORMING THE SAME
App. No. 12/410,789
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METHOD FOR REDUCING DIELECTRIC OVERETCH WHEN MAKING CONTACT TO CONDUCTIVE FEATURES
App. No. 12/363,588
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THREE TERMINAL NONVOLATILE MEMORY DEVICE WITH VERTICAL GATED DIODE
App. No. 12/320,351
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RESIST FEATURE AND REMOVABLE SPACER PITCH DOUBLING PATTERNING METHOD FOR PILLAR STRUCTURES
App. No. 12/318,609
→
METHODS AND DEVICES FOR FORMING NANOSTRUCTURE MONOLAYERS AND DEVICES INCLUDING SUCH MONOLAYERS
App. No. 12/291,101
→
SYSTEM AND METHOD FOR AC VOLTAGE REGULATION
App. No. 12/229,543
→
METHOD OF MAKING A NONVOLATILE MEMORY DEVICE INCLUDING FORMING A PILLAR SHAPED SEMICONDUCTOR DEVICE AND A SHADOW MASK
App. No. 12/216,924
→
NON-VOLATILE MEMORY AND METHOD WITH CONTROL GATE COMPENSATION FOR SOURCE LINE BIAS ERRORS
App. No. 12/143,015
→
MEMORY DEVICE FOR PROTECTING MEMORY CELLS DURING PROGRAMMING
App. No. 12/140,991
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METHOD FOR FABRICATING SELF-ALIGNED COMPLEMENTARY PILLAR STRUCTURES AND WIRING
App. No. 12/149,151
→
METHODS OF FABRICATING NON-VOLATILE MEMORY WITH INTEGRATED SELECT AND PERIPHERAL CIRCUITRY AND POST-ISOLATION MEMORY CELL FORMATION
App. No. 12/061,642
→
METHODS OF FABRICATING NON-VOLATILE MEMORY WITH INTEGRATED PERIPHERAL CIRCUITRY AND PRE-ISOLATION MEMORY CELL FORMATION
App. No. 12/061,641
→
INTEGRATED NON-VOLATILE MEMORY AND PERIPHERAL CIRCUITRY FABRICATION
App. No. 12/058,512
→
ALTERNATE SENSING TECHNIQUES FOR NON-VOLATILE MEMORIES
App. No. 12/023,317
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METHODS AND APPARATUS FOR FORMING MEMORY LINES AND VIAS IN THREE DIMENSIONAL MEMORY ARRAYS USING DUAL DAMASCENE PROCESS AND IMPRINT LITHOGRAPHY
App. No. 11/967,638
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METHOD OF MAKING A PILLAR PATTERN USING TRIPLE OR QUADRUPLE EXPOSURE
App. No. 12/005,276
→
METHOD FOR FABRICATING PITCH-DOUBLING PILLAR STRUCTURES
App. No. 12/000,758
→
Nano-Enabled Memory Devices and Anisotropic Charge Carrying Arrays
App. No. 11/850,127
→
METHODS AND DEVICES FOR FORMING NANOSTRUCTURE MONOLAYERS AND DEVICES INCLUDING SUCH MONOLAYERS
App. No. 11/881,739
→
SEMICONDUCTOR DIE HAVING A REDISTRIBUTION LAYER
App. No. 11/769,937
→
METHOD OF FABRICATING A SEMICONDUCTOR DIE HAVING A REDISTRIBUTION LAYER
App. No. 11/769,927
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Nano-enabled memory devices and anisotropic charge carrying arrays
App. No. 11/766,980
→
THREE-DIMENSIONAL MEMORY DEVICE INCORPORATING SEGMENTED ARRAY LINE MEMORY ARRAY
App. No. 11/764,789
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SMART VERIFY FOR MULTI-STATE MEMORIES
App. No. 11/759,872
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METHOD OF FABRICATING A SELF-ALIGNING DAMASCENE MEMORY STRUCTURE
App. No. 11/786,620
→
NANO-ENABLED MEMORY DEVICES AND ANISOTROPIC CHARGE CARRYING ARRAYS
App. No. 11/695,728
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POST-DEPOSITION ENCAPSULATION OF NANOSTRUCTURES: COMPOSITIONS, DEVICES AND SYSTEMS INCORPORATING SAME
App. No. 11/706,730
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FLASH MEMORY ARRAY WITH INCREASED COUPLING BETWEEN FLOATING AND CONTROL GATES
App. No. 11/668,306
→
NON-VOLATILE MEMORY AND METHOD WITH COMPENSATION FOR SOURCE LINE BIAS ERRORS
App. No. 11/624,617
→
NON-VOLATILE MEMORY AND METHOD WITH CONTROL GATE COMPENSATION FOR SOURCE LINE BIAS ERRORS
App. No. 11/624,627
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SPACER PATTERNS USING ASSIST LAYER FOR HIGH DENSITY SEMICONDUCTOR DEVICES
App. No. 11/623,315
→
METHODS OF FORMING SPACER PATTERNS USING ASSIST LAYER FOR HIGH DENSITY SEMICONDUCTOR DEVICES
App. No. 11/623,314
→
SEMICONDUCTOR DEVICE HAVING MULTIPLE DIE REDISTRIBUTION LAYER
App. No. 11/617,687
→
METHOD OF MAKING A SEMICONDUCTOR DEVICE HAVING MULTIPLE DIE REDISTRIBUTION LAYER
App. No. 11/617,689
→
METHOD OF FORMING A FLASH NAND MEMORY CELL ARRAY WITH CHARGE STORAGE ELEMENTS POSITIONED IN TRENCHES
App. No. 11/614,894
→
FLASH NAND MEMORY CELL ARRAY WITH CHARGE STORAGE ELEMENTS POSITIONED IN TRENCHES
App. No. 11/614,909
→
METHOD FOR ISOTROPIC DOPING OF A NON-PLANAR SURFACE EXPOSED IN A VOID
App. No. 11/610,090
→
METHOD FOR PROTECTING MEMORY CELLS DURING PROGRAMMING
App. No. 11/552,441
→
MEMORY DEVICE FOR PROTECTING MEMORY CELLS DURING PROGRAMMING
App. No. 11/552,426
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Dense arrays and charge storage devices
App. No. 11/544,666
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METHOD FOR NON-VOLATILE MEMORY WITH REDUCED ERASE/WRITE CYCLING DURING TRIMMING OF INITIAL PROGRAMMING VOLTAGE
App. No. 11/531,217
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NON-VOLATILE MEMORY WITH REDUCED ERASE/WRITE CYCLING DURING TRIMMING OF INITIAL PROGRAMMING VOLTAGE
App. No. 11/531,223
→
NON-VOLATILE MEMORY WITH LINEAR ESTIMATION OF INITIAL PROGRAMMING VOLTAGE
App. No. 11/531,230
→
METHOD FOR NON-VOLATILE MEMORY WITH LINEAR ESTIMATION OF INITIAL PROGRAMMING VOLTAGE
App. No. 11/531,227
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NON-VOLATILE MEMORY WITH ASYMMETRICAL DOPING PROFILE
App. No. 11/469,281
→
METHODS OF FORMING NONVOLATILE MEMORIES WITH L-SHAPED FLOATING GATES
App. No. 11/465,038
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NONVOLATILE MEMORIES WITH SHAPED FLOATING GATES
App. No. 11/465,025
→