Method for reducing dielectric overetch when making contact to conductive features
A method is provided that includes forming conductive or semiconductive features above a first dielectric material, depositing a second dielectric material above the conductive or semiconductive features, etching a void in the second dielectric material, wherein the etch stops on the first dielectric material, and exposing a portion of the conductive or semiconductive features. Numerous other aspects are provided.
1. A method comprising:
forming conductive or semiconductive features above a first dielectric material;
depositing a second dielectric material above the conductive or semiconductive features;
etching a void in the second dielectric material, wherein the etch stops on the first dielectric material; and
exposing a portion of the conductive or semiconductive features,
wherein the conductive or semiconductive features comprise a monolithic three dimensional memory array.
2. The method of claim 1 , wherein the conductive or semiconductive features comprise a metal and/or a semiconductor material.
3. The method of claim 1 , wherein the first dielectric material comprises one or more of silicon nitride, silicon carbide, and silicon oxynitride.
4. The method of claim 1 , wherein the second dielectric material comprises silicon dioxide.
5. The method of claim 1 , wherein the second dielectric material is deposited on a substantially planar surface, the substantially planar surface coexposing the first dielectric material and the conductive or semiconductive features.
6. A method comprising:
forming at least semiconductive features above and in contact with a first dielectric material;
forming a second dielectric material above and contacting the at least semiconductive features;
etching a void in the second dielectric material, wherein the etch stops on the first dielectric material; and
exposing a portion of the at least semiconductive features,
wherein the at least semiconductive features are elements in a monolithic three dimensional memory array.
7. The method of claim 6 , wherein the first dielectric material comprises one or more of silicon nitride, silicon carbide, and silicon oxynitride.
8. The method of claim 6 , wherein the second dielectric material comprises silicon dioxide.
9. The method of claim 6 , wherein forming the at least semiconductive features comprises:
depositing a layer or stack of conductive or semiconductor material; and
patterning and etching the layer or stack of at least semiconductive material to form the at least semiconductive features.
10. The method of claim 6 , wherein the second dielectric material is deposited on a substantially planar surface, the substantially planar surface coexposing the first dielectric material and the at least semiconductive features.
11. A method comprising:
forming a first device level by:
forming conductive features;
forming a first dielectric layer on the conductive features;
depositing a second dielectric material above the conductive features;
etching a void in the second dielectric material, wherein the etch stops on the first dielectric material; and
forming a via within the void, the via making electrical connection to one of the conductive features; and
monolithically forming at least a second device level above the first device level.
12. The method of claim 11 , wherein the conductive features comprise a metal and/or a semiconductor material.
13. The method of claim 11 , wherein the conductive features comprise rail-shaped conductors.
14. The method of claim 11 , wherein the first device level comprises a first memory level of memory cells.
15. The method of claim 11 , wherein the second device level comprises a second memory level of memory cells.
16. The method of claim 11 , wherein the first dielectric material comprises one or more of silicon nitride, silicon carbide, and silicon oxynitride.
17. The method of claim 11 , wherein the second dielectric material comprises silicon dioxide.
18. The method of claim 11 , wherein the second dielectric material is deposited on a substantially planar surface, the substantially planar surface coexposing the first dielectric material and the conductive features.