Three-dimensional memory device incorporating segmented array line memory array
View Patent ↗A three-dimensional (3D) high density memory array includes multiple layers of segmented bit lines (i.e., sense lines) with segment switch devices within the memory array that connect the segments to global bit lines. The segment switch devices reside on one or more layers of the integrated circuit, preferably residing on each bit line layer. The global bit lines reside preferably on one layer below the memory array, but may reside on more than one layer. The bit line segments preferably share vertical connections to an associated global bit line. In certain EEPROM embodiments, the array includes multiple layers of segmented bit lines with segment connection switches on multiple layers and shared vertical connections to a global bit line layer. Such memory arrays may be realized with much less write-disturb effects for half selected memory cells, and may be realized with a much smaller block of cells to be erased.
1. An integrated circuit, comprising:
a memory array, said memory array includes a first memory layer, said first memory layer includes a first bit line segment coupled to a first set of memory cells, said first memory layer includes a first segment switch device coupled to said first bit line segment;
a global bit line, said global bit line is coupled to said first segment switch device; and
a column decoder, said column decoder is coupled to said global bit line, a portion of said column decoder is arranged under said memory array; wherein:
said memory array includes a second memory layer, said second memory layer includes a second bit line segment coupled to a second set of memory cells, said second memory layer includes a second segment switch device coupled to said second bit line segment, said second memory layer is arranged above said first memory layer; and
said global bit line is coupled to said second segment switch device.
2. The integrated circuit of claim 1 , wherein:
said global bit line includes a shared vertical connection.
3. The integrated circuit of claim 1 , wherein:
said first set of memory cells includes a SONOS device.
4. The integrated circuit of claim 1 , wherein:
said first set of memory cells includes a passive element memory cell.
5. The integrated circuit of claim 1 , wherein:
said first segment switch device includes a MOS transistor.
6. The integrated circuit of claim 1 , wherein:
said memory array comprises a half-mirrored array.
7. The integrated circuit of claim 1 , wherein:
said memory array comprises a fully-mirrored array.
8. The integrated circuit of claim 1 , wherein:
said memory array comprises a crosspoint array.