Method for reducing dielectric overetch when making contact to conductive features
View Patent ↗In a first aspect, a method is provided that includes: forming a plurality of conductive or semiconductive features above a first dielectric material; depositing a second dielectric material above the conductive or semiconductive features; etching a void in the second dielectric material, wherein the etch is selective between the first and the second dielectric material and the etch stops on the first dielectric material; and exposing a portion of the conductive or semiconductive features. Numerous other aspects are provided.
1. A method comprising:
forming a plurality of conductive or semiconductive features above a first dielectric material;
depositing a second dielectric material above the conductive or semiconductive features;
etching a void in the second dielectric material, wherein the etch is selective between the first and the second dielectric material and the etch stops on the first dielectric material; and
exposing a portion of the conductive or semiconductive features,
wherein the conductive or semiconductive features comprise a monolithic three dimensional memory array.
2. The method of claim 1 , wherein the conductive or semiconductive features comprise a metal.
3. The method of claim 2 , wherein the metal comprises tungsten or a tungsten alloy or compound.
4. The method of claim 1 , wherein the conductive or semiconductive features comprise semiconductor material.
5. The method of claim 1 , wherein the first dielectric material comprises one or more of silicon nitride, silicon carbide, and silicon oxynitride.
6. The method of claim 1 , wherein the second dielectric material comprises silicon dioxide.
7. The method of claim 1 , wherein the second dielectric material is deposited on a substantially planar surface, the substantially planar surface coexposing the first dielectric material and the conductive or semiconductive features.
8. A method comprising:
forming at least semiconductive features above and in contact with a first dielectric material;
forming a second dielectric material above and contacting the at least semiconductive features;
etching a void in the second dielectric material, wherein the etch is selective between the first and second dielectric material, and the etch stops on the first dielectric material; and
exposing a portion of the at least semiconductive features,
wherein the at least semiconductive features are elements in a monolithic three dimensional memory array.
9. The method of claim 8 , wherein the first dielectric material comprises one or more of silicon nitride, silicon carbide, and silicon oxynitride.
10. The method of claim 8 , wherein the second dielectric material comprises silicon dioxide.
11. The method of claim 8 , wherein forming the at least semiconductive features comprises:
depositing a layer or stack of conductive or semiconductor material; and
patterning and etching the layer or stack of at least semiconductive material to form the at least semiconductive features.
12. The method of claim 8 , wherein the second dielectric material is deposited on a substantially planar surface, the substantially planar surface coexposing the first dielectric material and the at least semiconductive features.
13. A method comprising:
forming a first device level comprising first conductive features;
forming a first dielectric layer in contact with the first conductive features;
depositing a second dielectric material above the first conductive features;
etching a void in the second dielectric material, wherein the etch is selective between the first dielectric material and the second dielectric material, wherein the etch stops on the first dielectric material;
exposing a portion of the first conductive features;
forming the via within the void, the via making electrical connection to a first conductive feature; and
monolithically forming at least a second device level above the first device level.
14. The method of claim 13 , wherein the first conductive features comprise a layer or stack of metal or deposited semiconductor material.
15. The method of claim 13 , wherein the first conductive features comprise rail-shaped conductors.
16. The method of claim 13 , wherein the first device level comprises a first memory level of memory cells.
17. The method of claim 13 , wherein the second device level comprises a second memory level of memory cells.
18. The method of claim 13 , wherein the first conductive features comprise a metal.
19. The method of claim 18 , wherein the metal comprises tungsten or a tungsten alloy or compound.
20. The method of claim 13 , wherein the first dielectric material comprises one or more of silicon nitride, silicon carbide, and silicon oxynitride.
21. The method of claim 13 , wherein the second dielectric material comprises silicon dioxide.
22. The method of claim 13 , wherein the second dielectric material is deposited on a substantially planar surface, the substantially planar surface coexposing the first dielectric material and the at least semiconductive features.