Patterning of submicron pillars in a memory array
Methods in accordance with the invention involve patterning and etching very small dimension pillars, such as in formation of a memory array in accordance with the invention. When dimensions of pillars become very small, the photoresist pillars used to pattern them may not have sufficient mechanical strength to survive the photoresist exposure and development process. Using methods according to the present invention, these photoresist pillars are printed and developed larger than their intended final dimension, such that they have increased mechanical strength, then are shrunk to the desired dimension during a preliminary etch performed before the etch of underlying material begins.
1. A method for forming a memory array, the method comprising:
forming a conductor rail above a substrate, the conductor rail having a rail width;
forming a layer of etchable material above the conductor rail;
forming a layer of photoresist over the etchable material;
patterning and developing the photoresist to form a plurality of photoresist pillars, each photoresist pillar having a first width less than about 0.3 micron and larger than the rail width, wherein the plurality of photoresist pillars are configured with the first width to survive mechanical stresses encountered prior to an etching;
shrinking the photoresist pillars to a shrunk width smaller than the first width and substantially equal to the rail width;
etching the etchable material to form a plurality of etched pillars, wherein each etched pillar is substantially aligned with the conductor rail and has a width substantially equal to the rail width; and
forming the memory array comprising a plurality of memory cells, wherein each memory cell comprises one of the etched pillars.
2. The method of claim 1 , wherein the shrunk width is less than about 95 percent of the first width.
3. The method of claim 2 , wherein the shrunk width is less than about 90 percent of the first width.
4. The method of claim 1 , wherein the shrunk width is at least about 0.01 micron less than the first width.
5. The method of claim 4 , wherein the shrunk width is at least about 0.02 micron less than the first width.
6. The method of claim 1 , wherein each memory cell comprises a vertically oriented diode.
7. The method of claim 6 , wherein each vertically oriented diode comprises one of the etched pillars.
8. The method of claim 1 , further comprising forming a layer of bottom antireflective coating between the layer of etchable material and the layer of photoresist.
9. The method of claim 8 , further comprising etching the layer of bottom antireflective coating during the shrinking step.
10. A method for forming a monolithic three dimensional memory array, the method comprising:
a) forming a first memory level by a method comprising:
i) forming a conductor rail above a substrate, the conductor rail having a rail width;
ii) forming a first etchable layer above the conductor rail;
iii) forming a photoresist layer over the first etchable layer;
iv) patterning and developing the photoresist layer to form photoresist pillars, each pillar having a first width larger than the rail width, wherein each pillar is configured with the first width to survive mechanical stresses encountered prior to an etching;
v) shrinking the photoresist pillars until each pillar has a second width, the second width less than the first width, and wherein the second width is substantially equal to the rail width; and
vi) etching the first etchable layer to form etched pillars, wherein each etched pillar is substantially aligned with the conductor rail, and has a width substantially equal to the rail width; and
b) monolithically forming a second memory level above the first memory level.
11. The method of claim 10 , wherein the first width is the largest patterned dimension of each photoresist pillar.
12. The method of claim 11 , wherein the first width is less than about 0.3 micron.
13. The method of claim 12 , wherein the second width is less than about 95 percent of the first width.
14. The method of claim 13 , wherein the second width is less than about 90 percent of the first width.
15. The method of claim 10 , wherein the second width is at least about 0.01 micron less than the first width.
16. The method of claim 15 , wherein the second width is at least about 0.02 micron less than the first width.
17. The method of claim 10 , wherein the first memory level comprises a first plurality of memory cells, each first memory cell comprising one of the etched pillars.
18. The method of claim 17 , wherein each memory cell comprises a diode.
19. The method of claim 18 , wherein the monolithic three dimensional memory array is a nonvolatile one-time programmable memory array.
20. The method of claim 10 , further comprising forming a layer of bottom antireflective coating between the first etchable layer and the layer of photoresist.
21. The method of claim 20 , further comprising etching the layer of bottom antireflective coating during the shrinking step.