Non-volatile memory with linear estimation of initial programming voltage
In a non-volatile memory, a selected page on a word line is successively programmed by a series of voltage pulses of a staircase waveform with verifications in between the pulses until the page is verified to a designated pattern. The programming voltage at the time the page is programmed verified will be to estimate the initial value of a starting programming voltage for the page. The estimation is further refined by using the estimate from a first pass in a second pass. Also, when the test is over multiple blocks, sampling of word lines based on similar geometrical locations of the blocks can yield a starting programming voltage optimized for faster programming pages.
1. A non-volatile memory comprising:
an array of memory cells that is organized into erasable blocks, each erasable block containing a block of word lines for accessing memory cells that are erasable together, and each word line containing at least one page of memory cells that are programmable together;
a designated sample of pages representative of the given page within a block;
an associated programming voltage for programming each page of the sample, the associated programming voltage having a staircase waveform with an initial value and a predetermined maximum voltage limit;
a built-in self testing module for determining a starting programming voltage for a given page, said module providing memory operations including:
(a) erasing the sample of pages;
(b) for every page in the sample, programming and verifying the page step by step of the staircase waveform until either the maximum voltage limit has been reached or the page has been programmed to a target pattern and in which case a final programming voltage is accumulated as part of a gathered statistics; and
(c) providing the gathered statistic for computing an average starting programming voltage for the sample for deriving a starting programming voltage for the given page; and wherein:
the sample is part of larger sample taken from a plurality of blocks in the memory array; and
the gathered statistics includes accumulated initial values associated with programmable pages from the plurality of blocks.
2. The memory as in claim 1 , wherein the nonvolatile memory is of the NAND type.
3. The memory as in claim 1 , wherein individual memory cells each stores more than one bit of data.
4. A non-volatile memory comprising:
an array of memory cells that is organized into erasable blocks, each erasable block containing a block of word lines for accessing memory cells that are erasable together, and each word line containing at least one page of memory cells that are programmable together;
a designated sample of pages representative of the given page within a block;
an associated programming voltage for programming each page of the sample, the associated programming voltage having a staircase waveform with an initial value and a predetermined maximum voltage limit;
a built-in self-testing module for determining a starting programming voltage for a given page, said module providing memory operations including:
(a) erasing the sample of pages;
(b) for every page in the sample, programming and verifying the page step by step of the staircase waveform until either the maximum voltage limit has been reached or the page has been programmed to a target pattern and in which case a final programming voltage is accumulated as part of a gathered statistics; and
(c) providing the gathered statistic for computing an average starting programming voltage for the sample for deriving a starting programming voltage for the given page; and wherein said module provides memory operations further including:
forming a set of samples by selecting a page from each block, the page being located in a geometrically similar location of each block;
obtaining a statistical estimation of a programming voltage from each sample of the set; and
wherein the step of computing an average starting programming voltage for the sample is by selecting a minimum statistical estimation among the set.
5. The memory as in claim 4 , wherein the nonvolatile memory is of the NAND type.
6. The memory as in claim 4 , wherein individual memory cells each stores more than one bit of data.