Patent Assignment
Reel/Frame 038809/0472
CHANGE OF NAME
Recorded: 2016-05-25
Received: 2016-05-25
Pages: 17
Assignor
SANDISK TECHNOLOGIES INC
Executed: 2016-05-16
Assignee
SANDISK TECHNOLOGIES LLC
6900 DALLAS PARKWAY, SUITE 325, PLANO, TX, 75024, UNITED STATES
Covered Applications
(100)
CONTROLLER BASED MEMORY EVALUATION
App. No. 13/943,516
→
Light Therapy Monitoring
App. No. 13/939,217
→
NAND FLASH MEMORY WITH FIXED CHARGE
App. No. 11/692,958
→
METHODS OF FORMING NAND FLASH MEMORY WITH FIXED CHARGE
App. No. 11/692,961
→
FLASH MEMORY WITH DATA REFRESH TRIGGERED BY CONTROLLED SCRUB DATA READS
App. No. 11/692,829
→
FLASH MEMORY REFRESH TECHNIQUES TRIGGERED BY CONTROLLED SCRUB DATA READS
App. No. 11/692,840
→
METHOD TO PROGRAM A MEMORY CELL COMPRISING A CARBON NANOTUBE FABRIC AND A STEERING ELEMENT
App. No. 11/692,144
→
THREE DIMENSIONAL NAND MEMORY
App. No. 11/691,901
→
METHOD OF MAKING THREE DIMENSIONAL NAND MEMORY
App. No. 11/691,840
→
LARGE ARRAY OF UPWARD POINTING P-I-N DIODES HAVING LARGE AND UNIFORM CURRENT
App. No. 11/692,153
→
METHOD OF MAKING THREE DIMENSIONAL NAND MEMORY
App. No. 11/691,917
→
THREE DIMENSIONAL NAND MEMORY
App. No. 11/691,939
→
MEMORY CELL COMPRISING A CARBON NANOTUBE FABRIC ELEMENT AND A STEERING ELEMENT
App. No. 11/692,148
→
METHOD OF MAKING THREE DIMENSIONAL NAND MEMORY
App. No. 11/691,885
→
METHOD TO FORM UPWARD POINTING P-I-N DIODES HAVING LARGE AND UNIFORM CURRENT
App. No. 11/692,151
→
METHOD OF MAKING THREE DIMENSIONAL NAND MEMORY
App. No. 11/691,858
→
ON-CHIP DATA GROUPING AND ALIGNMENT
App. No. 11/690,253
→
SCALABLE SELF-ALIGNED DUAL FLOATING GATE MEMORY CELL ARRAY AND METHODS OF FORMING THE ARRAY
App. No. 11/689,775
→
ADJUSTING RESISTANCE OF NON-VOLATILE MEMORY USING DUMMY MEMORY CELLS
App. No. 11/688,874
→
DE-GLITCH CIRCUIT
App. No. 11/686,828
→
SELECTIVELY POWERED DATA INTERFACES
App. No. 11/686,350
→
METHOD FOR CACHE PAGE COPY IN A NON-VOLATILE MEMORY
App. No. 11/683,356
→
NON-VOLATILE MEMORY WITH CACHE PAGE COPY
App. No. 11/683,365
→
SYSTEM FOR REDUCING READ DISTURB FOR NON-VOLATILE STORAGE
App. No. 11/681,188
→
METHOD OF PLASMA ETCHING TRANSITION METAL OXIDES
App. No. 11/681,022
→
FLASH EEPROM SYSTEM WITH SIMULTANEOUS MULTIPLE DATA SECTOR PROGRAMMING AND STORAGE OF PHYSICAL BLOCK CHARACTERISTICS IN OTHER DESIGNATED BLOCKS
App. No. 11/679,012
→
PCB CIRCUIT MODIFICATION FROM MULTIPLE TO INDIVIDUAL CHIP ENABLE SIGNALS
App. No. 11/679,157
→
METHOD OF MAKING PCB CIRCUIT MODIFICATION FROM MULTIPLE TO INDIVIDUAL CHIP ENABLE SIGNALS
App. No. 11/679,153
→
Electronic Library for Managing Data on Removable Storage Devices
App. No. 11/677,388
→
COMPENSATING FOR COUPLING IN NON-VOLATILE STORAGE
App. No. 11/675,632
→
NON-VOLATILE MEMORY READ OPERATIONS USING COMPENSATION CURRENTS
App. No. 11/675,545
→
TIME-DEPENDENT COMPENSATION CURRENTS IN NON-VOLATILE MEMORY READ OPERATIONS
App. No. 11/675,551
→
REDUCING THE EFFECTS OF NOISE IN NON-VOLATILE MEMORIES THROUGH MULTIPLE READS
App. No. 11/674,000
→
MULTIPLE REMOVABLE NON-VOLATILE MEMORY CARDS SERIALLY COMMUNICATING WITH A HOST
App. No. 11/673,958
→
WRITE PROTECTION AND USE OF ERASE TAGS IN A SINGLE HOST MULTIPLE CARDS SYSTEM
App. No. 11/673,957
→
FLASH CONTROLLER CACHE ARCHITECTURE
App. No. 11/671,394
→
CABLING FOR RACK-MOUNT DEVICES
App. No. 11/670,309
→
METHODS AND APPARATUS FOR EMPLOYING REDUNDANT ARRAYS TO CONFIGURE NON-VOLATILE MEMORY
App. No. 11/669,918
→
METHODS AND APPARATUS FOR USING A CONFIGURATION ARRAY SIMILAR TO AN ASSOCIATED DATA ARRAY
App. No. 11/669,919
→
METHODS AND APPARATUS FOR USING A CONFIGURATION ARRAY SIMILAR TO AN ASSOCIATED DATA ARRAY
App. No. 11/669,923
→
EMBEDDED MEMORY IN A CMOS CIRCUIT AND METHODS OF FORMING THE SAME
App. No. 11/669,859
→
EMBEDDED MEMORY IN A CMOS CIRCUIT AND METHODS OF FORMING THE SAME
App. No. 11/669,850
→
METHODS AND APPARATUS FOR EMPLOYING REDUNDANT ARRAYS TO CONFIGURE NON-VOLATILE MEMORY
App. No. 11/669,917
→
FLASH MEMORY ARRAY WITH INCREASED COUPLING BETWEEN FLOATING AND CONTROL GATES
App. No. 11/668,306
→
NAND MEMORY WITH VIRTUAL CHANNEL
App. No. 11/626,778
→
METHODS OF FORMING NAND MEMORY WITH VIRTUAL CHANNEL
App. No. 11/626,784
→
NON-VOLATILE MEMORY AND METHOD WITH COMPENSATION FOR SOURCE LINE BIAS ERRORS
App. No. 11/624,617
→
CUSTOMIZED NON-VOLATILE MEMORY DEVICE PACKAGES
App. No. 11/624,610
→
NON-VOLATILE MEMORY AND METHOD WITH CONTROL GATE COMPENSATION FOR SOURCE LINE BIAS ERRORS
App. No. 11/624,627
→
SPACER PATTERNS USING ASSIST LAYER FOR HIGH DENSITY SEMICONDUCTOR DEVICES
App. No. 11/623,315
→
METHODS OF FORMING SPACER PATTERNS USING ASSIST LAYER FOR HIGH DENSITY SEMICONDUCTOR DEVICES
App. No. 11/623,314
→
NON-VOLATILE MEMORY CELLS SHAPED TO INCREASE COUPLING TO WORD LINES
App. No. 11/622,634
→
NON-VOLATILE MEMORY AND METHOD WITH IMPROVED SENSING
App. No. 11/621,750
→
NAND FLASH MEMORY WITH A PROGRAMMING VOLTAGE HELD DYNAMICALLY IN A NAND CHAIN CHANNEL REGION
App. No. 11/621,190
→
CONNECTION BETWEEN AN I/O REGION AND THE CORE REGION OF AN INTEGRATED CIRCUIT
App. No. 11/651,614
→
NON-VOLATILE MEMORY AND METHOD WITH REDUCED SOURCE LINE BIAS ERRORS
App. No. 11/620,946
→
EXPANDABLE AND COLLAPSIBLE PERIPHERAL DEVICE
App. No. 11/620,519
→
NOVEL METHOD AND STRUCTURE FOR EFFICIENT DATA VERIFICATION OPERATION FOR NON-VOLATILE MEMORIES
App. No. 11/619,991
→
MEMORY DEVICE WITH IMPROVED TEMPERATURE-SENSOR CIRCUIT
App. No. 11/649,569
→
VOLTAGE BUFFER FOR CAPACITIVE LOADS
App. No. 11/620,001
→
FLEXIBLE AND AREA EFFICIENT COLUMN REDUNDANCY FOR NON-VOLATILE MEMORIES
App. No. 11/619,524
→
SELECTIVE OPERATION OF A MULTI-STATE NON-VOLATILE MEMORY SYSTEM IN A BINARY MODE
App. No. 11/619,533
→
USE OF DATA LATCHES IN CACHE OPERATIONS OF NON-VOLATILE MEMORIES
App. No. 11/619,513
→
ANALOG VOLTAGE GENERATOR WITH SELF-BIASED CAPACITIVE FEEDBACK STAGE
App. No. 11/618,918
→
GENERATION OF ANALOG VOLTAGE USING SELF-BIASED CAPACITIVE FEEDBACK STAGE
App. No. 11/618,917
→
METHOD FOR USING A REVERSIBLE POLARITY DECODER CIRCUIT
App. No. 11/618,843
→
METHOD FOR USING A MULTIPLE POLARITY REVERSIBLE CHARGE PUMP CIRCUIT
App. No. 11/618,838
→
REVERSIBLE POLARITY DECODER CIRCUIT
App. No. 11/618,844
→
SYSTEMS AND METHODS FOR IDENTIFYING AND BOOTING A COMPUTER ARCHITECTURE
App. No. 11/618,872
→
METHOD FOR PERFORMING FULL TRANSFER AUTOMATION IN A USB CONTROLLER
App. No. 11/618,865
→
MULTIPLE POLARITY REVERSIBLE CHARGE PUMP CIRCUIT
App. No. 11/618,841
→
NON-VOLATILE STORAGE WITH BIAS FOR TEMPERATURE COMPENSATION
App. No. 11/618,786
→
NON-VOLATILE STORAGE WITH BIAS BASED ON SELECTED WORD LINE
App. No. 11/618,790
→
BIASING NON-VOLATILE STORAGE TO COMPENSATE FOR TEMPERATURE VARIATIONS
App. No. 11/618,782
→
BIASING NON-VOLATILE STORAGE BASED ON SELECTED WORD LINE
App. No. 11/618,788
→
IMAGING POST STRUCTURES USING X AND Y DIPOLE OPTICS AND A SINGLE MASK
App. No. 11/618,776
→
NON-VOLATILE STORAGE WITH ADAPTIVE BODY BIAS
App. No. 11/618,793
→
APPLYING ADAPTIVE BODY BIAS TO NON-VOLATILE STORAGE
App. No. 11/618,791
→
ELECTRICAL CONNECTOR WITH GROUNDING PIN
App. No. 11/618,084
→
SYSTEM FOR CODE EXECUTION
App. No. 11/618,526
→
SYSTEMS FOR PROGRAMMING NON-VOLATILE MEMORY WITH REDUCED PROGRAM DISTURB BY USING DIFFERENT PRE-CHARGE ENABLE VOLTAGES
App. No. 11/618,606
→
PAGE BY PAGE ECC VARIATION IN A MEMORY DEVICE
App. No. 11/618,694
→
PAGE BY PAGE ECC VARIATION IN A MEMORY DEVICE
App. No. 11/618,686
→
UNIFIED VOLTAGE GENERATION METHOD WITH IMPROVED POWER EFFICIENCY
App. No. 11/618,522
→
SYSTEM FOR CONTROLLING VOLTAGE IN NON-VOLATILE MEMORY SYSTEMS
App. No. 11/618,544
→
METHOD FOR CONTROLLING VOLTAGE IN NON-VOLATILE MEMORY SYSTEMS
App. No. 11/618,541
→
NAND FLASH MEMORY CELL ARRAY WITH ADAPTIVE MEMORY STATE PARTITIONING
App. No. 11/618,498
→
METHOD OF NAND FLASH MEMORY CELL ARRAY WITH ADAPTIVE MEMORY STATE PARTITIONING
App. No. 11/618,482
→
SYSTEMS FOR MARGINED NEIGHBOR READING FOR NON-VOLATILE MEMORY READ OPERATIONS INCLUDING COUPLING COMPENSATION
App. No. 11/618,624
→
RESISTANCE SENSING AND COMPENSATION FOR NON-VOLATILE STORAGE
App. No. 11/617,972
→
MARGINED NEIGHBOR READING FOR NON-VOLATILE MEMORY READ OPERATIONS INCLUDING COUPLING COMPENSATION
App. No. 11/618,616
→
ELECTRONIC DEVICE WITH A RETRACTABLE CONNECTOR AND PROTECTIVE DOOR MECHANISM
App. No. 11/618,447
→
ALTERNATING READ MODE
App. No. 11/618,569
→
METHOD FOR CODE EXECUTION
App. No. 11/618,519
→
APPARATUS WITH ALTERNATING READ MODE
App. No. 11/618,578
→
PROGRAMMING NON-VOLATILE MEMORY WITH REDUCED PROGRAM DISTURB BY USING DIFFERENT PRE-CHARGE ENABLE VOLTAGES
App. No. 11/618,600
→
HYBRID MASK AND METHOD OF MAKING SAME
App. No. 11/648,245
→
UNIFIED VOLTAGE GENERATION APPARATUS WITH IMPROVED POWER EFFICIENCY
App. No. 11/618,539
→
Methods for launching a program application
App. No. 11/647,995
→
METHOD OF MAKING AN ELECTRICAL CONNECTOR WITH ESD GROUNDING CLIP
App. No. 11/618,292
→