Connection between an I/O region and the core region of an integrated circuit
A connection between a first circuit within an I/O region of an integrated circuit chip and a second circuit within a core region of the chip. The first circuit is connected to a bonding pad through a first conductor in a first layer of an I/O region. The second circuit is connected to the bonding pad through a second conductor in a second layer of an I/O region above the first layer.
1. An integrated circuit chip comprising:
a core region having metal layers;
an I/O region between the core region and an edge of the chip, wherein the I/O region includes a first conductor in a first metal layer and a second conductor in a second metal layer;
a bonding pad within the I/O region, the bonding pad comprising a metal conductor at each of the metal layers, wherein the first conductor is connected to a first metal conductor of the bonding pad and the second conductor is connected to a second metal conductor of the bonding pad;
a first circuit within the I/O region, wherein the first circuit is connected to the first conductor at an input of the first circuit;
a second circuit within the core region and below all of the metal layers, wherein the second circuit is connected to the second conductor at an output of the second circuit; and
wherein a portion of the first circuit occupies a portion of the first metal layer of the I/O region between the first conductor and the core region so as to preclude a third conductor in the first metal layer of the I/O region from extending from the first conductor to the core region; and
wherein the first circuit is configured to receive a signal from the second circuit via the first and second conductors and the bonding pad.
2. The chip of claim 1 , wherein:
a portion of the first circuit occupies a portion of the first metal layer of the I/O region between the first conductor and the core region.
3. The chip of claim 1 , wherein:
the second circuit includes first and second inputs connected to receive first and second input signals, and wherein the second circuit is configured to produce the signal, that is received by the first circuit, at the output of the second circuit based on the values of the first and second inputs.
4. The chip of claim 1 , wherein:
the input of the first circuit comprises includes a power input;
the second circuit comprises a power control circuit including a control input connected to receive a control signal and a power input connected to receive a first voltage, wherein the output of the second circuit comprises and a power output at which the power control circuit supplies a second voltage and wherein the power control circuit controls the level of the second voltage in response to the control signal; and
the signal received by the first circuit comprises the power output of the power control circuit.
5. The chip of claim 4 , wherein:
the power control circuit is a power switch.
6. The chip of claim 4 , wherein:
the power control circuit is a voltage regulator.
7. The chip of claim 1 , wherein:
the second conductor extends between the I/O region and the core region.
8. The chip of claim 1 , further comprising a dielectric layer between the first and second metal layers.
9. The chip of claim 1 , wherein the second metal layer is above the first metal layer.
10. An integrated circuit chip comprising:
a core region having metal layers;
an I/O region between the core region and an edge of the chip, wherein the I/O region includes a first conductor and a second conductor vertically separated from the first conductor;
a bonding pad within the I/O region, wherein the bonding pad is electrically connected to the first and second conductors;
a first circuit within the I/O region, wherein the first circuit is connected to the said first conductor;
a second circuit within the core region and below all of the metal layers, wherein the second circuit is connected to the second conductor; and
wherein a portion of the first circuit occupies a portion of a the first metal layer of the I/O region between the first conductor and the core region so as to preclude a third conductor in the first metal layer of the I/O region from extending from the first conductor to the core region; and
wherein the first circuit is configured to receive a signal from the second circuit via the first and second conductors and the bonding pad.
11. The chip of claim 10 , wherein:
a portion of the first circuit occupies a portion of the first metal layer of the I/O region between the first conductor and the core region.
12. The chip of claim 10 , wherein:
the first circuit includes an input connected to said first conductor in the first metal layer of the I/O region; and
the second circuit includes an output connected to the second conductor in the second metal layer of the I/O region.
13. The chip of claim 10 , wherein:
the first circuit includes an input connected to said first conductor in the first metal layer of the I/O region;
the second circuit includes first and second inputs connected to receive first and second input signals and an output at which the second circuit produces an output signal, wherein the second circuit changes the value of the output signal in response to the respective values of the first and second input signals; and
the output of the second circuit is connected to the second conductor in the second metal layer of the I/O region.
14. The chip of claim 10 , wherein:
the first circuit includes a power input connected to said first conductor in the first metal layer of the I/O region;
the second circuit comprises a power control circuit including a control input connected to receive a control signal, a power input connected to receive a first voltage, and a power output at which the power control circuit supplies a second voltage, wherein the power control circuit controls the level of the second voltage in response to the control signal; and
the power output of the power control circuit is connected to the second conductor in the second metal layer of the I/O region.
15. The chip of claim 14 , wherein:
the power control circuit is a power switch.
16. The chip of claim 14 , wherein:
the power control circuit is a voltage regulator.
17. The chip of claim 10 , wherein:
the first circuit includes an output connected to said first conductor in the first metal layer of the I/O region; and
the second circuit includes an input connected to the second conductor in the second metal layer of the I/O region.
18. The chip of claim 10 , wherein:
the second conductor extends between the I/O region and the core region.
19. The chip of claim 10 , further comprising a dielectric layer between the first and second layers.
20. The chip of claim 10 , wherein the second conductor is above the first conductor.
21. An integrated circuit chip comprising:
a core region having metal layers;
an I/O region between the core region and an edge of the chip, wherein the I/O region includes a first conductor in a first metal layer and a second conductor in a second metal layer;
a bonding pad within the I/O region, the bonding pad comprising a metal conductor at each of the metal layers, wherein the first conductor is connected to a first metal conductor of the bonding pad and the second conductor is connected to a second metal conductor of the bonding pad;
a crystal oscillator within the I/O region, wherein the crystal oscillator is connected to the first conductor at a power input of the crystal oscillator;
a voltage regulator within the core region, wherein the voltage regulator is connected to the second conductor at a power output of the voltage regulator; and
wherein a portion of the crystal oscillator occupies a portion of the first metal layer of the I/O region between the first conductor and the core region so as to preclude a third conductor in the first metal layer of the I/O region from extending from the first conductor to the core region; and
wherein the crystal oscillator is configured to receive a signal from the voltage regulator via the first and second conductors and the bonding pad.