Method of making three dimensional NAND memory
A method of making a monolithic, three dimensional NAND string, includes forming a semiconductor active region of a first memory cell over a semiconductor active region of a second memory cell. The semiconductor active region of the first memory cell is a first pillar having a square or rectangular cross section when viewed from above, the first pillar being a first conductivity type semiconductor region located between second conductivity type semiconductor regions. The semiconductor active region of the second memory cell is a second pillar having a square or rectangular cross section when viewed from above, the second pillar located under the first pillar, the second pillar being a first conductivity type semiconductor region located between second conductivity type semiconductor regions. One second conductivity type semiconductor region in the first pillar contacts one second conductivity type semiconductor region in the second pillar.
1. A method of making a monolithic, three dimensional array of semiconductor devices, comprising:
forming a plurality of second semiconductor pillar active regions in a second device level, wherein the second semiconductor pillar active regions are separated from each other by insulating material regions;
epitaxially growing a first semiconductor layer on the second semiconductor pillar active regions and on the insulating material regions, such that grain boundary regions in the first semiconductor layer are located over the insulating material regions;
planarizing the first semiconductor layer;
patterning the first semiconductor layer into a plurality of first strips extending in a first direction;
forming a first insulating layer between the plurality of first strips;
patterning the first semiconductor layer to remove the grain boundary regions and to leave a plurality of substantially single crystal first semiconductor pillar active regions in a first device level by patterning the plurality of first strips and the first insulating layer to form the plurality of the first semiconductor pillar active regions;
forming a first charge storage dielectric film in spaces between the first semiconductor pillar active regions, wherein the first charge storage dielectric film comprises one or more trenches; and
filling the trenches in the first charge storage dielectric film with first word lines; wherein the array of semiconductor devices comprises an array of vertical NAND strings.
2. The method of claim 1 , wherein each of the first semiconductor pillar active regions comprise a first conductivity type semiconductor region located between second conductivity type semiconductor regions.
3. The method of claim 2 , further comprising:
planarizing the first charge storage dielectric film and the first word lines;
partially etching the first word lines;
forming a first insulating cap layer over the partially etched first word lines;
planarizing the first insulating cap layer to expose the first semiconductor pillar active regions; and
forming bit lines in contact with the first semiconductor pillar active regions.
4. The method of claim 1 , further comprising:
forming a plurality of select transistors on a substrate or in trenches in the substrate, wherein the plurality of select transistors comprise a plurality of third semiconductor pillar active regions separated by insulating material regions;
epitaxially growing a second semiconductor layer on the third semiconductor pillar active regions and on the insulating material regions, such that grain boundary regions in the second semiconductor layer are located over the insulating material regions; and
patterning the second semiconductor layer to remove the grain boundary regions and to leave the plurality of second semiconductor pillar active regions in a second device level.
5. The method of claim 4 , further comprising:
planarizing the second semiconductor layer;
patterning the second semiconductor layer into a plurality of second strips extending in the first direction;
forming a second insulating layer between the plurality of second strips;
patterning the plurality of second strips and the second insulating layer to form the plurality of the second semiconductor pillar active regions, wherein each of the second semiconductor pillar active region comprises a first conductivity type semiconductor region located between second conductivity type semiconductor regions;
forming a second charge storage dielectric film in spaces between the second semiconductor pillar active regions, wherein the second charge storage dielectric film comprises one or more trenches;
filling the trenches in the second charge storage dielectric film with second word lines;
planarizing the second charge storage dielectric film and the second word lines;
partially etching the second word lines;
forming a second insulating cap layer over the partially etched second word lines; and
planarizing the second insulating cap layer to expose the second semiconductor pillar active regions separated by the insulating material regions.