Memory device with improved temperature-sensor circuit
View Patent ↗The preferred embodiments described below provide a method and memory device for improving the precision of a temperature-sensor circuit. In one preferred embodiment, first and second temperature-dependent reference voltages are generated and compared, and an operating condition of the memory array is controlled based on the result of the comparison. Instead of using a temperature-dependent reference voltage, a temperature-dependent reference current can be used. Other embodiments are disclosed, and each of the embodiments can be used alone or together in combination.
1. A memory device that controls an operating condition of a memory array based on temperature, the memory device comprising:
a memory array;
a first temperature-dependent reference voltage source operative to generate a first temperature-dependent reference voltage comprising a negative temperature coefficient;
a second temperature-dependent reference voltage source operative to generate a second temperature-dependent reference voltage comprising a positive temperature coefficient;
a comparator operative to compare the first temperature-dependent reference voltage with the second temperature-dependent reference voltage; and
a controller operative to control an operating condition of the memory array based on a result of the comparator.
2. The memory device of claim 1 further comprising:
a third temperature-dependent reference voltage source operative to generate a third temperature-dependent reference voltage comprising a positive temperature coefficient; and
a second comparator operative to compare the first temperature-dependent reference voltage with the third temperature-dependent reference voltage;
wherein the controller is further operative to control an operating condition of the memory array based on a result of the second comparator.
3. The memory device of claim 1 , wherein the controller is operative to control a programming bandwidth of the memory array based on a result of the comparison of the first and second temperature-dependent reference voltages.
4. The memory device of claim 3 , wherein the controller is operative to control an operating condition of the memory array by reducing programming bandwidth of the memory array if the second temperature-dependent reference voltage is greater than the first temperature-dependent reference voltage.
5. The memory device of claim 1 , wherein the controller is operative to control a read bandwidth of the memory array based on a result of the comparison of the first and second temperature-dependent reference voltages.
6. The memory device of claim 1 , wherein the controller is operative to control a voltage across a memory cell for read based on a result of the comparison of the first and second temperature-dependent reference voltages.
7. The memory device of claim 1 , wherein the controller is operative to control a voltage across a memory cell for write based on a result of the comparison of the first and second temperature-dependent reference voltages.
8. The memory device of claim 1 , wherein the controller is operative to control a sensing current for read based on a result of the comparison of the first and second temperature-dependent reference voltages.
9. The memory device of claim 1 , wherein the controller is operative to control a sensing time for read based on a result of the comparison of the first and second temperature-dependent reference voltages.
10. A memory device that controls an operating condition of a memory array based on temperature, the memory device comprising:
a memory array;
a first temperature-dependent reference current source operative to generate a first temperature-dependent reference current comprising a negative temperature coefficient;
a second temperature-dependent reference current source operative to generate a second temperature-dependent reference current comprising a positive temperature coefficient;
a comparator operative to compare the first temperature-dependent reference current with the second temperature-dependent reference current; and
a controller operative to control an operating condition of the memory array based on a result of the comparator.
11. The memory device of claim 10 , wherein the controller is operative to control a programming bandwidth of the memory array based on a result of the comparison of the first and second temperature-dependent reference currents.
12. The memory device of claim 10 , wherein the controller is operative to control a read bandwidth of the memory array based on a result of the comparison of the first and second temperature-dependent reference currents.
13. The memory device of claim 10 , wherein the controller is operative to control a voltage across a memory cell for read based on a result of the comparison of the first and second temperature-dependent reference currents.
14. The memory device of claim 10 , wherein the controller is operative to control a voltage across a memory cell for write based on a result of the comparison of the first and second temperature-dependent reference currents.
15. The memory device of claim 10 , wherein the controller is operative to control a sensing current for read based on a result of the comparison of the first and second temperature-dependent reference currents.
16. The memory device of claim 10 , wherein the controller is operative to control a sensing time for read based on a result of the comparison of the first and second temperature-dependent reference currents.