System for reducing read disturb for non-volatile storage
A system for reducing or removing a form of read disturb in a non-volatile storage device. One embodiment seeks to prevent read disturb by eliminating or minimizing boosting of the channel of the memory elements. For example, one implementation prevents or reduces boosting of the source side of the NAND string channel during a read process. Because the source side of the NAND string channel is not boosted, at least one form of read disturb is minimized or does not occur.
1. A non-volatile storage system, comprising:
a plurality of non-volatile storage elements;
a bit line in communication with said non-volatile storage elements; and
one or more managing circuits in communication with said non-volatile storage elements and said bit line, said one or more managing circuits establish read conditions for unselected non-volatile storage elements and prevent boosting of said non-volatile storage elements while setting up said read conditions, said one or more managing circuits determine data for a selected non-volatile storage element by sensing a change to said bit line after setting up said read conditions.
2. A non-volatile storage system according to claim 1 , wherein:
said one or more managing circuits establish read conditions by applying a read pass voltage to said unselected non-volatile storage elements.
3. A non-volatile storage system according to claim 1 , wherein:
said non-volatile storage elements are part of one or more NAND strings;
said establishing read conditions includes turning on select gates for said NAND strings and applying a pass voltage to word lines for said unselected non-volatile storage elements while said select gates are on; and
said one or more managing circuits include sense amplifiers in communication with bit lines for said NAND strings, said sensing is performed by said sense amplifiers.
4. A non-volatile storage system according to claim 1 , further comprising:
a first select gate in communication with said non-volatile storage elements and said one or more managing circuits, said one or more managing circuits prevent boosting by turning on a first select gate for said unselected non-volatile storage elements prior to said establishing read conditions and turning off said first select gate subsequent to said establishing read conditions but prior to said sensing data, said first select gate is connected to 0 volts.
5. A non-volatile storage system according to claim 4 , wherein:
said non-volatile storage elements are part of a NAND string;
said first select gate is a source side select gate;
said establishing conditions includes applying a read pass voltage to a subset of word lines for said NAND string while a drain side select gate is on; and
said one or more managing circuits include a sense amplifiers in communication with said bit line, said sensing is performed by using said sense amplifier.
6. A non-volatile storage system according to claim 1 , wherein:
said one or more managing circuits establish read conditions by applying a pass voltage to said unselected non-volatile storage elements; and
said one or more managing circuits prevent boosting by applying said read pass voltage as a control gate voltage to said selected non-volatile storage element while applying said read pass voltage to said unselected non-volatile storage elements and subsequently lowering said control gate voltage for said selected non-volatile storage element from said read pass voltage to a read compare voltage prior to said sensing.
7. A non-volatile storage system according to claim 6 , wherein:
said non-volatile storage elements are part of one or more NAND strings;
said establishing read conditions includes turning on a drain side select gate for said NAND string; and
said one or more managing circuits include sense amplifiers in communication with bit lines for said NAND strings, said sensing is performed by said sense amplifiers.
8. A non-volatile storage system according to claim 1 , wherein:
said plurality of non-volatile storage elements are multi-state flash memory devices; and
said one or more managing circuits establish read conditions, prevent boosting and sense data for different programming states.
9. A non-volatile storage system according to claim 1 , wherein:
said one or more managing circuits include one or more of a state machine, decoders, sense circuits, sense amplifiers and a controller.
10. A non-volatile storage system according to claim 1 , wherein:
said plurality of non-volatile storage elements are NAND flash memory devices.
11. A non-volatile storage system according to claim 1 , wherein:
said plurality of non-volatile storage elements include floating gates.
12. A non-volatile storage system, comprising:
a plurality of non-volatile storage elements;
a bit line in communication with said non-volatile storage elements; and
one or more managing circuits in communication with said non-volatile storage elements and said bit line, said one or more managing circuits establish read conditions for unselected non-volatile storage elements and prevent boosting of said non-volatile storage elements while setting up said read conditions, said one or more managing circuits determine data for a selected non-volatile storage element by sensing said bit line after setting up said read conditions.
13. A non-volatile storage system according to claim 12 , wherein:
said non-volatile storage elements are multi-state NAND flash memory devices.
14. A non-volatile storage system according to claim 12 , further comprising:
a first select gate in communication with said non-volatile storage elements and said one or more managing circuits, said one or more managing circuits prevent boosting by turning on said first select gate for said unselected non-volatile storage elements prior to said establishing read conditions and turning off said first select gate subsequent to said establishing read conditions but prior to said sensing data, said first select gate is connected to 0 volts.
15. A non-volatile storage system according to claim 14 , wherein:
said non-volatile storage elements are part of a NAND string;
said first select gate is a source side select gate;
said establishing conditions includes applying a read pass voltage to a subset of word lines for said NAND string while a drain side select gate is on; and
said one or more managing circuits include a sense amplifier in communication with said bit line, said sensing is performed by said sense amplifiers.
16. A non-volatile storage system according to claim 12 , wherein:
said one or more managing circuits establish read conditions by applying a pass voltage to said unselected non-volatile storage elements; and
said one or more managing circuits prevent boosting by applying said read pass voltage as a control gate voltage to said selected non-volatile storage element while applying said read pass voltage to said unselected non-volatile storage elements and subsequently lowering said control gate voltage for said selected non-volatile storage element from said read pass voltage to a read compare voltage prior to said sensing data.
17. A non-volatile storage system according to claim 16 , wherein:
said non-volatile storage elements are part of a NAND string that includes said selected non-volatile storage element and said unselected non-volatile storage elements;
said one or more managing circuits establish read conditions by turning on a drain side select gate for said NAND string; and
said one or more managing circuits include a sense amplifiers in communication with bit line, said sensing is performed by said sense amplifier.
18. A non-volatile storage system, comprising:
a NAND string, said NAND string includes a plurality of non-volatile storage elements;
a bit line connected to said NAND string; and
one or more managing circuits in communication with said NAND string and said bit line, said one or more managing circuits establish read conditions for unselected non-volatile storage elements of said NAND string and prevent boosting of said non-volatile storage elements while setting up said read conditions by providing a temporary path to ground for said NAND string while establishing said read conditions, said one or more managing circuits determine data for one of said non-volatile storage elements of said NAND string by sensing said bit line after setting up said read conditions.
19. A non-volatile storage system according to claim 18 , wherein:
said one or more managing circuits prevent boosting by turning on a first select gate for said unselected non-volatile storage elements prior to said establishing read conditions, and turning off said first select gate subsequent to said establishing read conditions but prior to said sensing data; and
said select gate is connected to 0 volts.
20. A non-volatile storage system according to claim 18 , wherein:
said one or more managing circuits establish read conditions by applying a pass voltage to said unselected non-volatile storage elements; and
said one or more managing circuits prevent boosting by applying said read pass voltage as a control gate voltage to said one of said non-volatile storage elements while applying said read pass voltage to said unselected non-volatile storage elements and subsequently lowering said control gate voltage for said selected non-volatile storage element from said read pass voltage to a read compare voltage prior to said sensing data.