Flash memory array with increased coupling between floating and control gates
View Patent ↗Floating gate structures are disclosed which have a base field coupled with the substrate and a narrow projection extending from the base away from the substrate. In one form, surfaces of a relatively large projection provide an increased surface area for a control gate that wraps around it, thereby increasing the coupling between the two. In another form, an erase gate wraps around a relatively small projection in order to take advantage of sharp edges of the projection to promote tunneling of electrons from the floating to the erase gate. In each case, the control or floating gate is positioned within the area of the floating gate in one direction, thereby not requiring additional substrate area for such memory cells.
1. A method of forming a nonvolatile memory array comprising:
forming a dielectric layer extending over a substrate surface;
forming a plurality of floating gates on the dielectric layer, each of the plurality of floating gates having an inverted-T shape in cross-section along a plane, an individual one of the plurality of floating gates has a lower portion in contact with the dielectric layer and an upper portion extending from the lower portion, the upper portion being narrower than a minimum process element size of a process used to form the nonvolatile memory array;
forming an intergate dielectric layer; and
forming a plurality of conductive gates that are elongated in a direction that is perpendicular to the plane, the plurality of conductive gates separated from the plurality of floating gates by the intergate dielectric layer.
2. The method of claim 1 wherein the plurality of floating gates and the plurality of conductive gates are self-aligned.
3. The method of claim 1 wherein an individual one of the plurality of conductive gates at least partially extends between neighboring ones of the plurality of floating gates.
4. The method of claim 1 wherein the lower portion has a dimension that is equal to the minimum process element size of the process used to form the nonvolatile memory array.
5. A method of forming a nonvolatile memory array comprising:
forming dielectric layer extending over a substrate surface;
forming a first conductive portion on the dielectric layer;
forming a plurality of projections that extend from the first conductive portion, each of the plurality of projections in electrical contact with the first conductive portion;
subsequently separating the first conductive portion to form a plurality of floating gates such that each of the plurality of floating gates includes a projection, each of the plurality of floating gates being wider than the projection in at least a first direction; and
forming a plurality of conductive control gates that extend in a second direction that is perpendicular to the first direction, the plurality of conductive control gates extending at least partially between neighboring ones of the plurality of floating gates; and
wherein each of the plurality of projections has a dimension in the first direction that is less than a minimum process element size.
6. The method of claim 5 wherein each of the plurality of projections has a dimension in the second direction that is equal to the minimum process element size.
7. The method of claim 5 wherein the plurality of conductive control gates and the plurality of floating gates are self-aligned.
8. The method of claim 5 further comprising forming an interlayer dielectric between the plurality of floating gates and the plurality of conductive control gates.
9. The method of claim 8 wherein the plurality of control gates are formed from a conductive layer that is deposited over the interlayer dielectric layer.