Methods of fabricating non-volatile memory with integrated select and peripheral circuitry and post-isolation memory cell formation

1. A method of making a non-volatile memory using a semiconductor substrate, the method comprising:

forming a first layer of dielectric material over a surface of the substrate;

forming a set of strips of charge storage material elongated in a first direction over the surface of the substrate with the first layer of dielectric material therebetween;

forming a set of strips of one or more additional layers over the first set of strips of charge storage material;

forming isolation trenches in the substrate elongated in the first direction between active areas of the substrate below the set of strips of charge storage material;

forming a pattern over the set of strips of charge storage material for etching a set of charge storage structures from each set;

covering a portion of the pattern with a cover;

etching at least one of said one or more additional layers while covering the portion of the pattern;

removing the cover from the portion of the pattern;

etching the set of strips of charge storage material using the pattern to form the sets of charge storage structures, wherein the charge storage structures of a set include sidewalls elongated in the first direction with spaces between sidewalls of structures adjacent in the second direction;

forming a second layer of dielectric material along the sidewalls of the set of charge storage structures; and

forming a set of strips of conductive material elongated in the second direction and at least partially occupying the spaces between adjacent charge storage structures.

2. The method of claim 1 , further comprising:

etching the set of strips of charge storage material after removing the cover to form a gate region for a select gate of each set, the gate region having a dimension in the first direction substantially equal to a dimension of the cover in the first direction.

3. The method of claim 2 , wherein:

the one or more additional layers include a first layer having a material composition substantially similar to a material composition of the pattern;

the first layer protects at least one different layer of the one or more additional layers during at least a portion of etching the set of strips of charge storage material.

4. The method of claim 2 , wherein the substrate includes a memory array region and a peripheral circuitry region, the pattern is formed at the memory array region of the substrate, the method further comprising:

applying a strip of resist material over the one or more additional layers at a portion of the peripheral circuitry region of the substrate;

wherein etching the at least one of the one or more additional layers is performed while said strip of resist material is over the portion of the peripheral circuitry region of the substrate.

5. The method of claim 4 , further comprising:

removing the strip of resist material;

etching the set of strips of charge storage material after removing the strip of resist material to form a gate region for at least one peripheral circuitry transistor associated with the sets of charge storage structures, the gate region having a dimension in the first direction substantially equal to a dimension of the strip of photoresist in the first direction.

6. The method of claim 1 , wherein:

the sets of charge storage structures are sets of conductive floating gate regions.

7. The method of claim 6 , wherein the sets of conductive floating gate regions are NAND strings of flash memory cells.

8. The method of claim 1 , wherein:

the strips of charge storage material include a first layer of polysilicon and a second layer of polysilicon;

etching the set of strips of charge storage material includes etching the second layer of polysilicon to form a second charge storage region for each charge storage structure and etching the first layer of polysilicon to form a first charge storage region for each charge storage structure;

wherein prior to etching the first layer of polysilicon, the method includes forming a set of spacers along the sidewalls of the second charge storage regions;

wherein etching the first layer of polysilicon includes using the set of spacers as a pattern such that a dimension of the second charge storage regions in the first direction is less than a dimension of the first charge storage regions in the first direction.

9. The method of claim 8 , wherein:

the first layer of polysilicon is doped polysilicon;

the second layer of polysilicon is undoped polysilicon; and

the strips of conductive material are undoped polysilicon.

10. The method of claim 1 , wherein the strips of conductive material are continuous in the second direction across the sets of charge storage structures thereby intrinsically forming word lines for the sets of charge storage structures.

11. The method of claim 1 , wherein the one or more additional layers are formed prior to forming the isolation trenches.

12. The method of claim 1 , wherein the one or more additional layers include a first layer formed prior to forming the isolation trenches and a second layer formed after forming the isolation trenches.