DENSE ARRAYS AND CHARGE STORAGE DEVICES
There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.
1 . An array of memory cells comprising:
a plurality of cells having at least one semiconductor region and a storage region for trapping charge; and
a control means for controlling the flow of current through the semiconductor region and the storage region.
2 . The array defined by claim 1 , wherein the control means is disposed in the cells.
3 . The array defined by claim 1 , wherein the at least one semiconductor region is N type.
4 . The array defined by claim 3 , wherein the control means comprises a P type semiconductor region and is disposed adjacent the N type semiconductor region.
5 . The array defined by claim 4 , wherein the storage means includes an oxide region.
6 . The array defined by claim 5 , wherein the storage means includes a nitrogen compound.
7 . The array defined by claim 1 , wherein the control means is disposed externally to the cells.
8 . The array defined by claim 1 , wherein the semiconductor regions of the cells are disposed in a substrate.
9 . The array defined by claim 1 , wherein semiconductor regions of the cells are formed of polysilicon.
10 . The array defined by claim 4 , wherein the control means comprises an n-channel, field-effect transistor which includes the n-type region.