Method for forming doped polysilicon via connecting polysilicon layers
View Patent ↗The invention provides for polysilicon vias connecting conductive polysilicon layers formed at different heights. Polysilicon vias are advantageously used in a monolithic three dimensional memory array of charge storage transistors. Polysilicon vias according to the present invention can be used, for example, to connect the channel layer of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells formed above the first device level. Similarly, vias according to the present invention can be used to connect the wordline of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells.
1. A method for forming a via structure to connect device levels in a monolithic three dimensional array, the method comprising:
providing a substrate;
forming a first device level of thin film transistors at a first height above the substrate, the first device level comprising a first polysilicon layer, the first polysilicon layer is a gate electrode of a thin film transistor of the first device level of thin film transistors;
forming a polysilicon via above the first polysilicon layer, a bottom surface of the polysilicon via is in contact with the first polysilicon layer; and
forming a second device level of thin film transistors at a second height above the substrate, wherein the second height is above the first height, the second device level comprising a second polysilicon layer,
wherein the second polysilicon layer is above the polysilicon via, and a top surface of the polysilicon via is in contact with the second polysilicon layer.
2. The method of claim 1 , wherein the monolithic three dimensional array is an array of memory cells.
3. The method of claim 2 , wherein the memory cells comprise charge storage memory cells.
4. The method of claim 3 , wherein the charge storage memory cells comprise SONOS-type memory cells.
5. The method of claim 3 , wherein the charge storage memory cells comprise floating gate memory cells.
6. The method of claim 1 , wherein the step of forming a polysilicon via comprises:
forming a layer of dielectric material;
etching a void in the layer of dielectric material;
filling the void with in situ doped polysilicon; and
planarizing the dielectric material and the in situ doped polysilicon to form a shared top surface.
7. The method of claim 1 , wherein the substrate comprises monocrystalline silicon.