Method for forming doped polysilicon via connecting polysilicon layers
View Patent ↗The invention provides for polysilicon vias connecting conductive polysilicon layers formed at different heights. Polysilicon vias are advantageously used in a monolithic three dimensional memory array of charge storage transistors. Polysilicon vias according to the present invention can be used, for example, to connect the channel layer of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells formed above the first device level. Similarly, vias according to the present invention can be used to connect the wordline of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells.
1. A method for forming a via structure in a semiconductor device, the method comprising:
forming a polysilicon via through a dielectric material;
planarizing a shared top surface of the polysilicon via and the dielectric material;
forming an upper polysilicon layer on and in contact with the polysilicon via; and
annealing the polysilicon via and the upper polysilicon layer such that dopant atoms diffuse from the polysilicon via to the upper polysilicon layer.
2. A method for forming a via structure in a semiconductor device, the method comprising:
forming a polysilicon via through a dielectric material;
planarizing a shared top surface of the polysilicon via and the dielectric material; and
forming an upper polysilicon layer on and in contact with the polysilicon via; wherein:
the step of forming the polysilicon via comprises:
depositing the dielectric material;
etching a void in the dielectric material; and
depositing in-situ doped polysilicon in the void; and
the step of forming the upper polysilicon layer comprises:
depositing a polysilicon film;
patterning and etching the polysilicon film to form a channel layer; and
doping a portion of the channel layer by ion implantation.
3. The method of claim 2 , wherein the step of planarizing a shared top surface of the polysilicon via and the dielectric material comprises an etchback step.
4. The method of claim 3 , wherein the etchback step comprises a first stage etch and a second stage etch, wherein the first stage etch removes excess polysilicon, and the second stage etch etches both polysilicon and the dielectric material.
5. The method of claim 4 , wherein the second stage etch has lower selectivity between polysilicon and the dielectric material than the first stage etch.
6. The method of claim 1 , wherein the upper polysilicon layer is a portion of a first device level of thin film transistors formed above a substrate.
7. The method of claim 6 , wherein at least a second device level of thin film transistors is monolithically formed above the first device level.
8. The method of claim 7 , wherein the first device level of thin film transistors comprises a plurality of charge storage memory cells.
9. The method of claim 8 , wherein the plurality of charge storage memory cells comprise SONOS-type memory cells.
10. The method of claim 8 , wherein the plurality of charge storage memory cells comprise floating gate memory cells.
11. The method of claim 6 , wherein the substrate comprises monocrystalline silicon.
12. The method of claim 2 , wherein the step of planarizing a shared top surface of the polysilicon via and the dielectric material comprises a CMP step.
13. A method for forming a via structure in a semiconductor device, the method comprising:
forming a polysilicon via through a dielectric material;
planarizing a shared top surface of the polysilicon via and the dielectric material;
forming an upper polysilicon layer on and in contact with the polysilicon via; and
before the step of forming a polysilicon via, forming a lower polysilicon layer below the polysilicon via, wherein the lower polysilicon layer is in contact with the polysilicon via;
wherein the step of forming the lower polysilicon layer comprises:
depositing a polysilicon film;
patterning and etching the polysilicon film to form a channel layer; and
doping the channel layer by ion implantation.