Method and apparatus for programming a memory array
View Patent ↗A method and apparatus for programming a memory array are disclosed. In one embodiment, after each word line is programmed, an attempt is made to detect a defect on that word line. If a defect is detected, the word line is repaired with a redundant word line. The word lines are then reprogrammed and rechecked for defects. In another embodiment, after each word line is programmed, an attempt is made to detect a defect on that word line. If a defect is detected, that word line is repaired along with a previously-programmed adjacent word line. In yet another embodiment, after each word line is programmed, an attempt is made to detect a defect on that word line and a previously-programmed adjacent word line. If a defect is detected on that word line, that word line and the previously-programmed adjacent word line are repaired with redundant word lines.
1. A method for programming a memory array, the method comprising:
(a) programming first and second word lines in a memory array, wherein the first word line comprises a defect that is detectable only after the second word line is programmed;
(b) after each word line is programmed:
(b1) attempting to detect a defect on that word line; and
(b2) if a defect is detected, repairing that word line with a redundant word line; and
(c) repeating (a) and (b), whereby the defect on the first word line is detected and the first word line is repaired the second time (a) and (b) are performed.
2. The method of claim 1 , wherein the defect on the second word line is detected and the second word line is repaired the first time (a) and (b) are performed.
3. The method of claim 1 , wherein the first word line is adjacent to the second word line in the memory array.
4. The method of claim 1 , wherein the memory array comprise a plurality of write-once memory cells.
5. The method of claim 4 , wherein the write-once memory cells comprises anti-fuse memory cells.
6. The method of claim 1 , wherein the memory array comprises a three-dimensional memory array comprising a plurality of memory cell layers stacked vertically above one another above a single silicon substrate.
7. The method of claim 1 , wherein (a) comprises programming first and second word lines and at least one additional word line in the memory array.
8. The method of claim 1 , wherein (b1) comprises reading information stored in that word line and comparing the read information with information stored in a buffer.
9. A method for programming a memory array, the method comprising:
(a) programming a plurality of word lines in a memory array; and
(b) after each word line is programmed,
(b1) attempting to detect a defect on that word line; and
(b2) if a defect is detected, repairing that word line and a previously-programmed adjacent word line with redundant word lines, whereby the previously-programmed adjacent word line is repaired even though a defect on the previously-programmed adjacent word line was not detected after the previously-programmed adjacent word line was programmed.
10. The method of claim 9 , wherein (b2) comprises if a defect is detected, repairing that word line, a previously-programmed adjacent word line, and a yet-to-be-programmed adjacent word line with redundant word lines.
11. The method of claim 9 , wherein the memory array comprise a plurality of write-once memory cells.
12. The method of claim 11 , wherein the write-once memory cells comprises anti-fuse memory cells.
13. The method of claim 9 , wherein the memory array comprises a three-dimensional memory array comprising a plurality of memory cell layers stacked vertically above one another above a single silicon substrate.
14. The method of claim 9 , wherein (b1) comprises reading information stored in that word line and comparing the read information with information stored in a buffer.
15. A method for programming a memory array, the method comprising:
(a) programming a plurality of word lines in a memory array; and
(b) after each word line is programmed,
(b1) attempting to detect a defect on that word line and a previously-programmed adjacent word line; and
(b2) if a defect is detected on that word line, repairing that word line and the previously-programmed adjacent word line with redundant word lines, whereby the previously-programmed adjacent word line is repaired even though a defect on the previously-programmed adjacent word line was not detected after the previously-programmed adjacent word line was programmed.
16. The method of claim 15 , wherein the memory array comprise a plurality of write-once memory cells.
17. The method of claim 16 , wherein the write-once memory cells comprises anti-fuse memory cells.
18. The method of claim 15 , wherein the memory array comprises a three-dimensional memory array comprising a plurality of memory cell layers stacked vertically above one another above a single silicon substrate.
19. The method of claim 15 , wherein (b1) comprises reading information stored in that word line and a previously-programmed adjacent word line and comparing the read information with information stored in a buffer.