Three-dimensional memory device with ECC circuitry
View Patent ↗The preferred embodiments described herein provide a memory device and methods for use therewith. In one preferred embodiment, a method is presented for using a file system to dynamically respond to variability in an indicated minimum number of memory cells of first and second write-once memory devices. In another preferred embodiment, a method for overwriting data in a memory device is described in which an error code is disregarded after a destructive pattern is written. In yet another preferred embodiment, a method is presented in which, after a block of memory has been allocated for a file to be stored in a memory device, available lines in that block are determined. Another preferred embodiment relates to reserving at least one memory cell in a memory device for file structures or file system structures. A memory device is also provided in which file system structures of at least two file systems are stored in the same memory partition. Additionally, methods for permanently preventing modification of data stored in a memory device and for identifying memory cells storing data are disclosed.
1. A three-dimensional memory device with ECC circuitry comprising:
a support element;
error checking and correcting (ECC) circuitry carried by the support element; and
a memory array carried by the support element, wherein the memory array comprises:
a first conductor;
a first memory cell above the first conductor;
a second conductor above the first memory cell; and
a second memory cell above the second conductor, wherein the first memory cell, second memory cell, and second conductor are all in a plane defined by the second conductor;
wherein the second conductor is the only conductor between the first and second memory cells in the plane.
2. The invention of claim 1 further comprising a housing protecting the error checking and correcting (ECC) circuitry and the memory array.
3. The invention of claim 1 , wherein the memory cells comprise write-once memory cells.
4. The invention of claim 1 , wherein the memory cells are selected from the group consisting of semiconductor-transistor-technology-based memory cells, magnetic-based memory cells, and organic-electronics-based memory cells.
5. A method for storing data and error checking and correcting (ECC) bits in a three-dimensional memory device with ECC circuitry, the method comprising:
(a) with a three-dimensional memory device comprising:
a support element;
error checking and correcting (ECC) circuitry carried by the support element; and
a memory array carried by the support element, wherein the memory array comprises:
a first conductor;
a first memory cell above the first conductor;
a second conductor above the first memory cell; and
a second memory cell above the second conductor, wherein the first memory cell, second memory cell, and second conductor are all in a plane defined by the second conductor;
wherein the second conductor is the only conductor between the first and second memory cells in the plane;
receiving at least one data bit to be stored in the memory array;
(b) with the ECC circuitry, generating at least one ECC bit based on the at least one data bit; and
(c) storing the at least one data bit and the at least one ECC bit in the memory array.
6. The invention of claim 5 further comprising:
(d) retrieving the at least one data bit and the at least one ECC bit in the memory array; and
(e) with the ECC circuitry, identifying an error in the retrieved at least one data bit and at least one ECC bit.
7. The invention of claim 5 , wherein the memory device further comprises a housing protecting the error checking and correcting (ECC) circuitry and the memory array.
8. The invention of claim 5 , wherein the memory cells comprise write-once memory cells.
9. The invention of claim 5 , wherein the memory cells are selected from the group consisting of semiconductor-transistor-technology-based memory cells, magnetic-based memory cells, and organic-electronics-based memory cells.
10. The invention of claim 1 , wherein the first memory cell is horizontally displaced from the second memory cell.
11. The invention of claim 1 , wherein the first memory cell is not horizontally displaced from the second memory cell.
12. The invention of claim 5 , wherein the first memory cell is horizontally displaced from the second memory cell.
13. The invention of claim 5 , wherein the first memory cell is not horizontally displaced from the second memory cell.