Apparatus and method for memory operations using address-dependent conditions
View Patent ↗An apparatus is disclosed comprising a plurality of word lines and word line drivers, a plurality of bit lines and bit line drivers, and a plurality of memory cells coupled between respective word lines and bit lines. The apparatus also comprises circuitry operative to select a writing and/or reading condition to apply to a memory cell based on the memory cell's location with respect to one or both of a word line driver and a bit line driver. The apparatus can also comprise circuitry that is operative to select a number of memory cells to be programmed in parallel based on memory cell location with respect to a word line and/or bit line driver.
1. An apparatus comprising:
a plurality of word lines and word line drivers;
a plurality of bit lines and bit line drivers;
a plurality of memory cells, wherein each memory cell is coupled between a respective word line and bit line; and
circuitry operative to select a writing condition to apply to a memory cell based on the memory cell's location with respect to one or both of a word line driver and a bit line driver;
wherein the circuitry is operative to select a different writing condition to apply to memory cells that are closer to the one or both of a word line driver and a bit line driver than to memory cells that are farther from the one or both of a word line driver and a bit line driver.
2. The invention of claim 1 , wherein the circuitry is operative to select a writing condition to apply to a memory cell based on the memory cell's location with respect to a word line driver but not to a bit line driver.
3. The invention of claim 1 , wherein the circuitry is operative to select a writing condition to apply to a memory cell based on the memory cell's location with respect to a bit line driver but not to a word line driver.
4. The invention of claim 1 , wherein the circuitry is operative to select a writing condition to apply to a memory cell based on the memory cell's location with respect to both a word line driver and a bit line driver.
5. The invention of claim 1 , wherein the circuitry is further operative to select a reading condition to apply to a memory cell based on the memory cell's location with respect to one or both of a word line driver and a bit line driver.
6. The invention of claim 1 , wherein the plurality of memory cells are organized into a plurality of zones, and wherein the circuitry is operative to select different writing conditions to apply to different zones.
7. The invention of claim 6 , wherein each zone comprises a plurality of word lines.
8. The invention of claim 6 , wherein each zone comprises a plurality of bit lines.
9. The invention of claim 6 , wherein each zone comprises a plurality of word lines and bit lines.
10. The invention of claim 1 , wherein each memory cell is associated with an address, and wherein the circuitry is operative to select a writing condition to apply to a memory cell based on the memory cell's address.
11. The invention of claim 1 , wherein at least some of the plurality of memory cells comprise write-once memory cells.
12. The invention of claim 1 , wherein at least some of the plurality of memory cells comprise write-many memory cells.
13. The invention of claim 1 , wherein at least some of the plurality of memory cells comprise few-time programmable memory cells.
14. The invention of claim 1 , wherein the plurality of memory cells are organized in a plurality of layers stacked vertically above one another above a single substrate.
15. The invention of claim 1 , wherein the plurality of memory cells are organized in a single layer.
16. An apparatus comprising:
a plurality of word lines and word line drivers;
a plurality of bit lines and bit line drivers;
a plurality of memory cells, wherein each memory cell is coupled between a respective word line and bit line; and
circuitry operative to select a writing condition to apply to a memory cell based on the memory cell's location with respect to one or both of a word line driver and a bit line driver;
wherein the writing condition comprises a voltage, and wherein the circuitry selects less of a voltage to apply to memory cells closer to the one or both of a word line driver and a bit line driver than to memory cells farther from the one or both of a word line driver and a bit line driver.
17. An apparatus comprising:
a plurality of word lines and word line drivers;
a plurality of bit lines and bit line drivers;
a plurality of memory cells, wherein each memory cell is coupled between a respective word line and bit line; and
circuitry operative to select a writing condition to apply to a memory cell based on the memory cell's location with respect to one or both of a word line driver and a bit line driver;
wherein the writing condition comprises a reference current, and wherein the circuitry selects a greater reference current to apply to memory cells closer to the one or both of a word line driver and a bit line driver than to memory cells farther from the one or both of a word line driver and a bit line driver.
18. An apparatus comprising:
a plurality of word lines and word line drivers;
a plurality of bit lines and bit line drivers;
a plurality of memory cells, wherein each memory cell is coupled between a respective word line and bit line; and
circuitry operative to select a writing condition to apply to a memory cell based on the memory cell's location with respect to one or both of a word line driver and a bit line driver;
wherein the writing condition comprises both a voltage and a reference current, wherein the circuitry selects less voltage and a greater reference current to apply to memory cells closer to the one or both of a word line driver and a bit line driver than to memory cells farther from the one or both of a word line driver and a bit line driver.
19. An apparatus comprising:
a plurality of word lines and word line drivers;
a plurality of bit lines and bit line drivers;
a plurality of memory cells, wherein each memory cell is coupled between a respective word line and bit line; and
circuitry operative to select a reading condition to apply to a memory cell based on the memory cell's location with respect to one or both of a word line driver and a bit line driver;
wherein the circuitry is operative to select a different reading condition to apply to memory cells that are closer to the one or both of a word line driver and a bit line driver than to memory cells that are farther from the one or both of a word line driver and a bit line driver.
20. The invention of claim 19 , wherein the circuitry is operative to select a reading condition to apply to a memory cell based on the memory cell's location with respect to a word line driver but not to a bit line driver.
21. The invention of claim 19 , wherein the circuitry is operative to select a reading condition to apply to a memory cell based on the memory cell's location with respect to a bit line driver but not to a word line driver.
22. The invention of claim 19 , wherein the circuitry is operative to select a reading condition to apply to a memory cell based on the memory cell's location with respect to both a word line driver and a bit line driver.
23. The invention of claim 19 , wherein the plurality of memory cells are organized into a plurality of zones, and wherein the circuitry is operative to select different reading conditions to apply to different zones.
24. The invention of claim 23 , wherein each zone comprises a plurality of word lines.
25. The invention of claim 23 , wherein each zone comprises a plurality of bit lines.
26. The invention of claim 23 , wherein each zone comprises a plurality of word lines and bit lines.
27. The invention of claim 19 , wherein each memory cell is associated with an address, and wherein the circuitry is operative to select a reading condition to apply to a memory cell based on the memory cell's address.
28. The invention of claim 19 , wherein at least some of the plurality of memory cells comprise write-once memory cells.
29. The invention of claim 19 , wherein at least some of the plurality of memory cells comprise write-many memory cells.
30. The invention of claim 19 , wherein at least some of the plurality of memory cells comprise few-time programmable memory cells.
31. The invention of claim 19 , wherein the plurality of memory cells are organized in a plurality of layers stacked vertically above one another above a single substrate.
32. The invention of claim 19 , wherein the plurality of memory cells are organized in a single layer.
33. An apparatus comprising:
a plurality of word lines and word line drivers;
a plurality of bit lines and bit line drivers;
a plurality of memory cells, wherein each memory cell is coupled between a respective word line and bit line; and
circuitry operative to select a reading condition to apply to a memory cell based on the memory cell's location with respect to one or both of a word line driver and a bit line driver;
wherein the reading condition comprises a voltage, and wherein the circuitry selects less of a voltage to apply to memory cells closer to the one or both of a word line driver and a bit line driver than to memory cells farther from the one or both of a word line driver and a bit line driver.
34. An apparatus comprising:
a plurality of word lines and word line drivers;
a plurality of bit lines and bit line drivers;
a plurality of memory cells, wherein each memory cell is coupled between a respective word line and bit line; and
circuitry operative to select a reading condition to apply to a memory cell based on the memory cell's location with respect to one or both of a word line driver and a bit line driver;
wherein the reading condition comprises a reference current, and wherein the circuitry selects a greater reference current to apply to memory cells closer to the one or both of a word line driver and a bit line driver than to memory cells farther from the one or both of a word line driver and a bit line driver.
35. An apparatus comprising:
a plurality of word lines and word line drivers;
a plurality of bit lines and bit line drivers;
a plurality of memory cells, wherein each memory cell is coupled between a respective word line and bit line; and
circuitry operative to select a reading condition to apply to a memory cell based on the memory cell's location with respect to one or both of a word line driver and a bit line driver;
wherein the reading condition comprises both a voltage and a reference current, wherein the circuitry select less of a voltage and a greater reference current to apply to memory cells closer to the one or both of a word line driver and a bit line driver than to memory cells farther from the one or both of a word line driver and a bit line driver.
36. An apparatus comprising:
a plurality of word lines and word line drivers;
a plurality of bit lines and bit line drivers;
a plurality of memory cells, wherein each memory cell is coupled between a respective word line and bit line; and
circuitry operative to select a number of memory cells to be programmed in parallel based on memory cell location with respect to one or both of a word line driver and a bit line driver;
wherein the circuitry is operative to select a different number of memory cells to be programmed in parallel for memory cells that are closer to the one or both of a word line driver and a bit line driver than for memory cells that are farther from the one or both of a word line driver and a bit line driver.
37. The invention of claim 36 , wherein the plurality of memory cells are organized into a plurality of zones, and wherein the circuitry is operative to select a number of memory cells to be programmed in parallel based on a memory cell's zone.
38. The invention of claim 37 , wherein each zone comprises a plurality of word lines.
39. The invention of claim 37 , wherein each zone comprises a plurality of bit lines.
40. The invention of claim 37 , wherein each zone comprises a plurality of word lines and bit lines.
41. The invention of claim 36 , wherein at least some of the plurality of memory cells comprise write-once memory cells.
42. The invention of claim 36 , wherein at least some of the plurality of memory cells comprise write-many memory cells.
43. The invention of claim 36 , wherein at least some of the plurality of memory cells comprise few-time programmable memory cells.
44. The invention of claim 36 , wherein the plurality of memory cells are organized in a plurality of layers stacked vertically above one another above a single substrate.
45. The invention of claim 36 , wherein the plurality of memory cells are organized in a single layer.