Reverse-bias method for writing memory cells in a memory array
A memory array having memory cells each comprising a diode and a phase change material or antifuse is reliably programmed by maintaining all word lines and bit lines connected to unselected memory cells at intermediate voltages and applying voltages to place the diode of a selected cell or cells in a reverse biased state and sufficient to program the phase change material or antifuse. Thus leakage through unselected cells is low so power wasted is small, and assurance is high that no unselected memory cells are disturbed.
1. In a memory array having memory cells at intersections of first lines and second lines, each memory cell having a diode cathode end connected to a first line and a diode anode end connected to a second line, each memory cell initially occupying a high resistance state, a method of programming the memory cells comprising:
applying a first voltage to at least one first line contacting the cathode end of at least one selected memory cell to be programmed to a different state;
applying a second voltage to first lines not contacting the cathode end of the at least one selected memory cell;
applying a third voltage to at least one second line contacting the anode end of at least one selected memory cell; and
applying a fourth voltage to second lines not contacting the anode end of the at least one selected memory cell;
wherein the first voltage is higher than the third voltage by an amount sufficient to program the at least one selected memory cell to a different state and the second and fourth voltages are at intermediate levels between the first and third voltages,
wherein further programming of the at least one selected memory cell is performed in which the first and third voltages are subsequently changed to cause current to pass through the diode in a forward biased direction, and
wherein the memory cells each include a diode in series with a state change element.
2. The method of programming the memory cells as in claim 1 , wherein the second and fourth voltages are equal.
3. The method of programming the memory cells as in claim 1 , wherein the second and fourth voltages are not equal.
4. The method of programming the memory cells as in claim 1 , wherein the second and fourth voltages are approximately half way between the first and third voltages.
5. The method of programming the memory cells as in claim 1 , wherein the further programming uses a higher current than was used during applying the first and third voltages.
6. The method of programming the memory cells as in claim 1 , wherein the further programming uses first and third voltages having a smaller voltage difference than was used during applying the first and third voltages to program the at least one selected memory cell to a different state.
7. The method of programming the memory cells as in claim 1 , wherein the state change element includes an antifuse.
8. The method of programming the memory cells as in claim 7 , wherein the antifuse is located at the diode cathode end.
9. In a memory array having memory cells at intersections of first lines and second lines, each memory cell having a diode cathode end connected to a first line and a diode anode end connected to a second line, each memory cell initially occupying a high resistance state, a method of programming the memory cells comprising:
applying a first voltage to at least one first line contacting the cathode end of at least one selected memory cell to be programmed to a different state;
applying a second voltage to first lines not contacting the cathode end of the at least one selected memory cell;
applying a third voltage to at least one second line contacting the anode end of at least one selected memory cell; and
applying a fourth voltage to second lines not contacting the anode end of the at least one selected memory cell,
wherein the first voltage is higher than the third voltage by an amount sufficient to program the at least one selected memory cell to a different state and the second and fourth voltages are at intermediate levels between the first and third voltages,
wherein the memory cells each include a diode and a state change element connected in series and wherein the state change element is located at the diode anode end.
10. The method of programming the memory cells as in claim 7 , wherein the diode is formed partially within a rail carrying a bit line and partially within a rail carrying a word line.
11. The method of programming the memory cells as in claim 7 , wherein the diode is formed in a pillar extending vertically between horizontal rails carrying a word line and a bit line.
12. The method of programming the memory cells as in claim 1 , wherein the state change element is a chalcogenide.
13. The method of programming the memory cells as in claim 12 , wherein the chalcogenide is at the cathode end.
14. The method of programming the memory cells as in claim 12 , wherein the chalcogenide is at the anode end.
15. The method of programming the memory cells as in claim 1 , wherein each of the memory cells comprises a diode having a high impedance forward biased state and a low impedance forward biased state.
16. The method of programming the memory cells as in claim 1 , wherein the at least one memory cell is one memory cell.
17. The method of programming the memory cells as in claim 1 , wherein the at least one memory cell is a plurality of memory cells comprising a word of memory.
18. The method of programming the memory cells as in claim 1 , wherein the first lines are bit lines and the second lines are word lines.
19. The method of programming the memory cells as in claim 1 , wherein the first lines are word lines and the second lines are bit lines.
20. In a memory array having memory cells each comprising a diode and a material with programmable resistance, the memory cells being arranged in an array of first and second programming lines, a method of programming the memory cells comprising:
applying a positive programming voltage to a first programming line connected to a cathode end of at least one selected memory cell and negative programming voltage to a second programming line connected to an anode end of the at least one selected memory cell; and
applying intermediate voltages to first and second programming lines not connected to cathode or anode ends of the at least one selected memory cell.
21. The method of programming the memory cells as in claim 20 , wherein the material with programmable resistance is an antifuse having initial high resistance that can be changed to a low resistance by the positive and negative programming voltages.
22. The method of programming the memory cells as in claim 20 , wherein the material with programmable resistance is a state change material having a resistance that is made high by a high current quickly removed and made low by a current lower than the high current that is removed more gradually than the high current.
23. The method of programming the memory cells as in claim 22 , wherein the state change material is a chalcogenide.
24. In a memory array having memory cells each comprising an antifuse and a diode, a method of programming the antifuse comprising:
passing current through the diode and antifuse in the reverse bias direction of the diode at sufficient voltage to cause the antifuse to rupture; and
passing current through the diode and antifuse in the forward bias direction of the diode at sufficient current and for sufficient time to cause the antifuse to develop a low resistance path.
25. The method of programming the memory cells as in claim 24 , wherein the steps are performed in the order stated.
26. The method of programming the memory cells as in claim 24 , further comprising applying to memory cells not sharing a bit line or word line with the antifuse an intermediate voltage insufficient to program the memory cells not sharing.
27. The method of programming the memory cells as in claim 9 , wherein the state change element is an antifuse.
28. The method of programming the memory cells as in claim 9 , wherein the state change element is a chalcogenide.