Nano-enabled memory devices and anisotropic charge carrying arrays
Methods and apparatuses for nanoenabled memory devices and anisotropic charge carrying arrays are described. In an aspect, a memory device includes a substrate, a source region of the substrate, and a drain region of the substrate. A population of nanoelements is deposited on the substrate above a channel region, the population of nanolements in one embodiment including metal quantum dots. A tunnel dielectric layer is formed on the substrate overlying the channel region, and a metal migration barrier layer is deposited over the dielectric layer. A gate contact is formed over the thin film of nanoelements. The nanoelements allow for reduced lateral charge transfer. The memory device may be a single or multistate memory device. In a multistate memory device which comprises one or more quantum dots or molecules having a plurality of discrete energy levels, a method is disclosed for charging and/or discharging the device which comprises filling each of the plurality of discrete energy levels of each dot or molecule with one or more electrons, and subsequently removing individual electrons at a time from each discrete energy level of the one or more dots or molecules.
1. A device in the stage of fabrication of a memory device, comprising:
a substrate;
a source region of said substrate;
a drain region of said substrate;
a channel region between said source and drain regions;
a charge storage layer comprising a population of nanoelements above said channel region, said nanoelements comprising colloidal metal nanoelements disposed in solution on said substrate, wherein the nanoelements each comprise one or more surface functional groups;
a dielectric layer deposited between said substrate and said charge storage layer; and
a barrier layer comprising nitrogen deposited or formed directly on said dielectric layer and adjacent to said charge storage layer.
2. The device of claim 1 , wherein said population of nanoelements includes a plurality of metal nanoparticles.
3. The device of claim 1 , wherein said metal nanoelements are made from a metal selected from the group comprising gold, palladium, iridium, platinum, ruthenium, cobalt, iron platinum alloy, and nickel.
4. The device of claim 1 , wherein the barrier layer comprises silicon nitride.